Rainbow-electronics MAX3679A Bedienungsanleitung PDF herunterladen (Seite 9)

MAX3679A

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+3.3V, Low-Jitter Crystal to LVPECL

Clock Generator

Interfacing with LVPECL Outputs

The equivalent LVPECL output circuit is given in Figure 8.

These outputs are designed to drive a pair of 50Ω trans-

mission lines terminated with 50Ω to V

- 2V. If a

separate termination voltage (V

) is not available, other

termination methods can be used such as shown in

Figures 5 and 6. Unused outputs should be disabled and

can be left open. For more information on LVPECL termi-

nations and how to interface with other logic families,

refer to Application Note 291:

HFAN-01.0: Introduction to

LVDS, PECL, and CML

Interface Models

Figures 7, 8, and 9 show examples of interface models.

MAX3679A

82Ω

= 50Ω

82Ω

130Ω 130Ω

+3.3V

HIGH

IMPEDANCE

Figure 5. Thevenin Equivalent of Standard PECL Termination

MAX3679A

150Ω

100Ω

= 50Ω

HIGH

IMPEDANCE

150Ω

0.1μF

NOTE: AC-COUPLING IS OPTIONAL.

0.1μF

Figure 6. AC-Coupled PECL Termination

14.5kΩ

ESD

STRUCTURES

REF_IN

= 1.4V

Figure 7. Simplified REF_IN Pin Circuit Schematic

ESD

STRUCTURES

Figure 8. Simplified LVPECL Output Circuit Schematic

10Ω

ESD

STRUCTURES

QA_CIN

DISABLE

DDO_A

Figure 9. Simplified LVCMOS Output Circuit Schematic

1 2 3 4 5 6 7 8 9 10 11

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