Rainbow-electronics ATA6831 Bedienungsanleitung

Features• Supply Voltage up to 40V• RDSon Typically 0.8Ω at 25°C, Maximum 1.5Ω at 150°C• Up to 1.0A Output Current• Three Half-bridge Outputs Formed b

104908D–AUTO–09/06ATA68313.6Thermal shutdown hysteresis∆Tj switch off15 K B3.7Ratio thermal shutdown off/thermal prewarning setTj switch off/ TjPW set

114908D–AUTO–09/06ATA68314.15High-side output switch on delay(1),(2)VVS = 13V RLoad=30Ωtdon20 µs A4.16Low-side output switch on delay(1),(2)VVS = 13V

124908D–AUTO–09/06ATA68319. Serial Interface TimingNo. Parameters Test Conditions Pin Timing Chart No.(1)Symbol Min. Typ. Max. Unit Type*8 Serial Inte

134908D–AUTO–09/06ATA6831Figure 9-1. Serial Interface Timing with Chart Number 1DOCSCLKCSDOCLKOutput DO: High level = 0.8 × VCC, low level = 0.2 × VCC

144908D–AUTO–09/06ATA683110. Application CircuitFigure 10-1. Application Circuit 10.1 Application Notes• Connect the blocking capacitors at VCC and VS

154908D–AUTO–09/06ATA683112. Package Information11. Ordering InformationExtended Type Number Package RemarksATA6831-PIQW QFN18, 4 mm × 4 mm Taped and

164908D–AUTO–09/06ATA683113. Revision HistoryPlease note that the following page numbers referred to in this section refer to the specific revision me

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,

24908D–AUTO–09/06ATA6831Figure 1-1. Block Diagram FaultdetectorFaultdetectorSIHS2LS2HS1LS1Controllogic5CLK6PWM7DO3CS4DIInput registerOuput registerSer

34908D–AUTO–09/06ATA68312. Pin ConfigurationFigure 2-1. Pinning QFN18 OUT3SOUT3FCSDICLKPWMOUT2FVS2VS1VCCGNDDOPGND3PGND1OUT1SOUT1FPGND2OUT2S12345612111

44908D–AUTO–09/06ATA68313. Functional Description3.1 Serial InterfaceData transfer starts with the falling edge of the CS signal. Data must appear at

54908D–AUTO–09/06ATA6831Table 3-2. Output Data ProtocolBitOutput (Status) Register Function0 TP Temperature prewarning: high = warning 1 Status LS1Nor

64908D–AUTO–09/06ATA6831After power-on reset, the input register has the following status:The following patterns are used to enable internal test mode

74908D–AUTO–09/06ATA68313.4 Overtemperature ProtectionIf the junction temperature of one or more output stages exceeds the thermal prewarning thresh-o

84908D–AUTO–09/06ATA68314. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the dev

94908D–AUTO–09/06ATA68317. Noise and Surge ImmunityParameters Test Conditions ValueConducted interferences ISO 7637-1 Level 4(1)Interference suppressi