Rainbow-electronics AT45DB011D Bedienungsanleitung

Features• Single 2.7V to 3.6V Supply• RapidS™Serial Interface: 66MHz Maximum Clock Frequency– SPI Compatible Modes 0 and 3• User Configurable Page Siz

103639J–DFLASH–11/2012AT45DB011D7.7 Chip EraseThe entire main memory can be erased at one time by using the Chip Erase command.To execute the Chip Era

113639J–DFLASH–11/2012AT45DB011D8. Sector ProtectionTwo protection methods, hardware and software controlled, are provided for protection againstinadv

123639J–DFLASH–11/2012AT45DB011DFigure 8-2. Disable Sector Protection8.1.3 Various Aspects About Software Controlled ProtectionSoftware controlled pro

133639J–DFLASH–11/2012AT45DB011D9.1 Sector Protection RegisterThe nonvolatile Sector Protection Register specifies which sectors are to be protected o

143639J–DFLASH–11/2012AT45DB011D9.1.1 Erase Sector Protection Register CommandIn order to modify and change the values of the Sector Protection Regist

153639J–DFLASH–11/2012AT45DB011D9.1.2 Program Sector Protection Register CommandOnce the Sector Protection Register has been erased, it can be reprogr

163639J–DFLASH–11/2012AT45DB011D9.1.3 Read Sector Protection Register CommandTo read the Sector Protection Register, theCS pin must first be asserted.

173639J–DFLASH–11/2012AT45DB011D10. Security Features10.1 Sector LockdownThe device incorporates a Sector Lockdown mechanism that allows each individu

183639J–DFLASH–11/2012AT45DB011D10.1.1 Sector Lockdown RegisterSector Lockdown Register is a nonvolatile register that contains 4-bytes of data, as sh

193639J–DFLASH–11/2012AT45DB011D10.2 Security RegisterThe device contains a specialized Security Register that can be used for purposes such asunique

23639J–DFLASH–11/2012AT45DB011DThe device is optimized for use in many commercial and industrial applications where high-den-sity, low-pin count, low-

203639J–DFLASH–11/2012AT45DB011D10.2.2 Reading the Security RegisterThe Security Register can be read by first asserting the CS pin and then clocking

213639J–DFLASH–11/2012AT45DB011D11.3 Auto Page RewriteThis mode is only needed if multiple bytes within a page or multiple pages of data are modified

223639J–DFLASH–11/2012AT45DB011Dthe data in the buffer. If bit six is a one, then at least one bit of the data in the main memory pagedoes not match t

233639J–DFLASH–11/2012AT45DB011D12.1 Resume from Deep Power-downThe Resume from Deep Power-down command takes the device out of the Deep Power-downmod

243639J–DFLASH–11/2012AT45DB011D13.1 Programming the Configuration RegisterTo program the Configuration Register for “power of 2” binary page size, th

253639J–DFLASH–11/2012AT45DB011D14.1 Manufacturer and Device ID InformationNote: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be

263639J–DFLASH–11/2012AT45DB011D14.2 Operation Mode SummaryThe commands described previously can be grouped into four different categories to betterde

273639J–DFLASH–11/2012AT45DB011D15. Command TablesTable 15-1. Read CommandsCommand OpcodeMain Memory Page Read D2HContinuous Array Read (Legacy Comman

283639J–DFLASH–11/2012AT45DB011DNote: 1. These legacy commands are not recommended for new designsTable 15-4. Additional CommandsCommand OpcodeMain Me

293639J–DFLASH–11/2012AT45DB011DNote: x = Don’t CareTable 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256-Bytes)Page Size = 256

33639J–DFLASH–11/2012AT45DB011DNote: 1. The metal pad on the bottom of the UDFN package is floating. This pad can be a “No Connect” or connected to GN

303639J–DFLASH–11/2012AT45DB011DNote: P = Page Address BitB = Byte/Buffer Address Bitx = Don’t CareTable 15-7. Detailed Bit-level Addressing Sequence

313639J–DFLASH–11/2012AT45DB011D16. Power-on/Reset StateWhen power is first applied to the device, or when recovering from a reset condition, the devi

323639J–DFLASH–11/2012AT45DB011D18. Electrical SpecificationsNotes: 1. ICC1during a buffer read is 20mA maximum @ 20MHz2. All inputs (SI, SCK,CS, WP,

333639J–DFLASH–11/2012AT45DB011DTable 18-4. AC Characteristics – RapidS/Serial InterfaceSymbol Parameter Min Typ Max UnitsfSCKSCK Frequency 66 MHzfCAR

343639J–DFLASH–11/2012AT45DB011D19. Input Test Waveforms and Measurement LevelstR,tF< 2ns (10% to 90%)20. Output Test Load21. AC WaveformsSix diffe

353639J–DFLASH–11/2012AT45DB011D21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz)21.2 Waveform 2 – SPI Mode 3 Compatible (for Freq

363639J–DFLASH–11/2012AT45DB011D21.5 Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability to operate at higher clock f

373639J–DFLASH–11/2012AT45DB011D21.6 Reset TimingNote: The CS signal should be in the high state before the RESET signal is deasserted21.7 Command Seq

383639J–DFLASH–11/2012AT45DB011D22. Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.22.1 Bu

393639J–DFLASH–11/2012AT45DB011D23. Read OperationsThe following block diagram and waveforms illustrate the various read sequences available.23.1 Main

43639J–DFLASH–11/2012AT45DB011D4. Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB011D is divided into three levels ofgranul

403639J–DFLASH–11/2012AT45DB011D23.3 Buffer Read24. Detailed Bit-level Read Waveform – RapidS Serial Interface Mode 0/Mode 324.1 Continuous Array Read

413639J–DFLASH–11/2012AT45DB011D24.3 Continuous Array Read (Low Frequency: Opcode 03H)24.4 Main Memory Page Read (Opcode: D2H)24.5 Buffer Read (Opcode

423639J–DFLASH–11/2012AT45DB011D24.6 Buffer Read (Low Frequency: Opcode D1H)24.7 Read Sector Protection Register (Opcode 32H)24.8 Read Sector Lockdown

433639J–DFLASH–11/2012AT45DB011D24.9 Read Security Register (Opcode 77H)24.10 Status Register Read (Opcode D7H)24.11 Manufacturer and Device Read (Opc

443639J–DFLASH–11/2012AT45DB011D25. Auto Page Rewrite FlowchartFigure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentiall

453639J–DFLASH–11/2012AT45DB011DFigure 25-2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of a DataFlash secto

463639J–DFLASH–11/2012AT45DB011D26. Ordering Information26.1 Ordering Code DetailNotes: 1. The shipping carrier option is not marked on the devices.2.

473639J–DFLASH–11/2012AT45DB011D27. Packaging Information27.1 8MA1 – UDFNTITLE DRAWING NO. GPC REV. Package Drawing Contact:[email protected]

483639J–DFLASH–11/2012AT45DB011D27.2 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE A1 0.10 –

493639J–DFLASH–11/2012AT45DB011D27.3 8S2 – EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawing Contact:[email protected] STN F 8S2, 8-lead, 0.

53639J–DFLASH–11/2012AT45DB011D6. Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or from theSRAM data buffer

503639J–DFLASH–11/2012AT45DB011D28. Revision HistoryRevision Level – Release Date HistoryA – June 2006 Initial ReleaseB – February 2007 Removed RDY/BU

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63639J–DFLASH–11/2012AT45DB011D(A16 - A0) and a dummy byte. Following the dummy byte, additional clock pulses on the SCKpin will result in data being

73639J–DFLASH–11/2012AT45DB011Doperation. Following the don’t care bytes, additional pulses on SCK result in data being outputon the SO (serial output

83639J–DFLASH–11/2012AT45DB011Dbytes), the opcode 83H must be clocked into the device followed by three address bytes consist-ing of seven don’t care

93639J–DFLASH–11/2012AT45DB011D7.6 Sector EraseThe Sector Erase command can be used to individually erase any sector in the main memory.There are four