Rainbow-electronics AT45DB081D Bedienungsanleitung

Features• Single 2.5V or 2.7V to 3.6V Supply• RapidS Serial Interface: 66MHz Maximum Clock Frequency– SPI Compatible Modes 0 and 3• User Configurable

103596N–DFLASH–11/2012AT45DB081D7.6 Sector EraseThe Sector Erase command can be used to individually erase any sector in the main memory.There are 16

113596N–DFLASH–11/2012AT45DB081DThe WP pin can be asserted while the device is erasing, but protection will not be activated untilthe internal erase c

123596N–DFLASH–11/2012AT45DB081D8.1 Software Sector Protection8.1.1 Enable Sector Protection CommandSectors specified for protection in the Sector Pro

133596N–DFLASH–11/2012AT45DB081DIf the device is power cycled, then the software controlled protection will be disabled. Once thedevice is powered up,

143596N–DFLASH–11/2012AT45DB081D9.1 Sector Protection RegisterThe nonvolatile Sector Protection Register specifies which sectors are to be protected o

153596N–DFLASH–11/2012AT45DB081DTable 9-4. Erase Sector Protection Register CommandFigure 9-2. Erase Sector Protection Register9.1.2 Program Sector Pr

163596N–DFLASH–11/2012AT45DB081DTable 9-5. Program Sector Protection Register CommandFigure 9-3. Program Sector Protection Register9.1.3 Read Sector P

173596N–DFLASH–11/2012AT45DB081D10. Security Features10.1 Sector LockdownThe device incorporates a Sector Lockdown mechanism that allows each individu

183596N–DFLASH–11/2012AT45DB081D10.1.1 Sector Lockdown RegisterSector Lockdown Register is a nonvolatile register that contains 16-bytes of data, as s

193596N–DFLASH–11/2012AT45DB081D10.2 Security RegisterThe device contains a specialized Security Register that can be used for purposes such asunique

23596N–DFLASH–11/2012AT45DB081Daddress lines and a parallel interface, the Adesto™DataFlash®uses a RapidS serial interface tosequentially access its d

203596N–DFLASH–11/2012AT45DB081D10.2.2 Reading the Security RegisterThe Security Register can be read by first asserting the CS pin and then clocking

213596N–DFLASH–11/2012AT45DB081Dcompletion of the compare operation, bit six of the status register is updated with the result ofthe compare.11.3 Auto

223596N–DFLASH–11/2012AT45DB081DThe result of the most recent Main Memory Page to Buffer Compare operation is indicated usingbit six of the status reg

233596N–DFLASH–11/2012AT45DB081D12.1 Resume from Deep Power-downThe Resume from Deep Power-down command takes the device out of the Deep Power-downmod

243596N–DFLASH–11/2012AT45DB081D13.1 Programming the Configuration RegisterTo program the Configuration Register for “power of 2” binary page size, th

253596N–DFLASH–11/2012AT45DB081D14.1 Manufacturer and Device ID InformationNote: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be

263596N–DFLASH–11/2012AT45DB081D14.2 Operation Mode SummaryThe commands described previously can be grouped into four different categories to betterde

273596N–DFLASH–11/2012AT45DB081D15. Command TablesTable 15-1. Read CommandsCommand OpcodeMain Memory Page Read D2HContinuous Array Read (Legacy Comman

283596N–DFLASH–11/2012AT45DB081DNote: 1. These legacy commands are not recommended for new designsRead Sector Lockdown Register 35HProgram Security Re

293596N–DFLASH–11/2012AT45DB081DNotes: x = Don’t CareTable 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (256-Bytes)Page Size = 25

33596N–DFLASH–11/2012AT45DB081DTable 2-1. Pin ConfigurationsSymbol Name and FunctionAssertedState TypeCSChip Select: Asserting theCS pin selects the d

303596N–DFLASH–11/2012AT45DB081DNotes: P = Page Address Bit B = Byte/Buffer Address Bit x = Don’t CareTable 15-7. Detailed Bit-level Addressing Sequen

313596N–DFLASH–11/2012AT45DB081D16. Power-on/Reset StateWhen power is first applied to the device, or when recovering from a reset condition, the devi

323596N–DFLASH–11/2012AT45DB081D18. Electrical SpecificationsNote: 1. After power is applied and VCCis at the minimum specified datasheet value, the s

333596N–DFLASH–11/2012AT45DB081DNotes: 1. ICC1during a buffer read is 20mA maximum @ 20MHz2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed

343596N–DFLASH–11/2012AT45DB081DTable 18-4. AC Characteristics – RapidS/Serial InterfaceSymbol ParameterAT45DB081D(2.5V Version) AT45DB081DMin Typ Max

353596N–DFLASH–11/2012AT45DB081D19. Input Test Waveforms and Measurement LevelstR,tF< 2 ns (10% to 90%)20. Output Test Load21. AC WaveformsSix diff

363596N–DFLASH–11/2012AT45DB081D21.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66MHz)21.2 Waveform 2 – SPI Mode 3 Compatible (for Freq

373596N–DFLASH–11/2012AT45DB081D21.5 Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability to operate at higher clock f

383596N–DFLASH–11/2012AT45DB081D21.6 Reset TimingNote: The CS signal should be in the high state before the RESET signal is deasserted21.7 Command Seq

393596N–DFLASH–11/2012AT45DB081D22. Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.22.1 Bu

43596N–DFLASH–11/2012AT45DB081D3. Block Diagram4. Memory ArrayTo provide optimal flexibility, the memory array of the AT45DB081D is divided into three

403596N–DFLASH–11/2012AT45DB081D23. Read OperationsThe following block diagram and waveforms illustrate the various read sequences available.23.1 Main

413596N–DFLASH–11/2012AT45DB081D23.3 Buffer Read24. Detailed Bit-level Read Waveform –RapidS Serial Interface Mode 0/Mode 324.1 Continuous Array Read

423596N–DFLASH–11/2012AT45DB081D24.3 Continuous Array Read (Low Frequency: Opcode 03H)24.4 Main Memory Page Read (Opcode: D2H)24.5 Buffer Read (Opcode

433596N–DFLASH–11/2012AT45DB081D24.6 Buffer Read (Low Frequency: Opcode D1H or D3H)24.7 Read Sector Protection Register (Opcode 32H)24.8 Read Sector L

443596N–DFLASH–11/2012AT45DB081D24.9 Read Security Register (Opcode 77H)24.10 Status Register Read (Opcode D7H)24.11 Manufacturer and Device Read (Opc

453596N–DFLASH–11/2012AT45DB081D25. Auto Page Rewrite FlowchartFigure 25-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentiall

463596N–DFLASH–11/2012AT45DB081DFigure 25-2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of an DataFlash sect

473596N–DFLASH–11/2012AT45DB081D26. Ordering Information26.1 Ordering Code DetailNotes: 1. The shipping carrier option is not marked on the devices.2.

483596N–DFLASH–11/2012AT45DB081D27. Packaging Information27.1 8M1-A – MLF (VDFN)TITLE DRAWING NO. GPC REV. Package Drawing Contact: contact@adesto

493596N–DFLASH–11/2012AT45DB081D27.2 8S1 – JEDEC SOICDRAWING NO. REV. TITLE GPCCOMMON DIMENSIONS(Unit of Measure = mm)SYMBOLMINNOMMAXNOTE A1 0.10 –

53596N–DFLASH–11/2012AT45DB081D5. Device OperationThe device operation is controlled by instructions from the host processor. The list of instructions

503596N–DFLASH–11/2012AT45DB081D27.3 8S2 – EIAJ SOICDRAWING NO. REV. TITLE GPC11NNEEqqCCE1E1LLAAbbA1A1eeDD Package Drawing Contact: contact@adesto

513596N–DFLASH–11/2012AT45DB081D28. Revision HistoryRevision Level – Release Date HistoryA – November 2005 Initial ReleaseB – March 2006Added Prelimin

523596N–DFLASH–11/2012AT45DB081D29. Errata29.1 No Errata Conditions

Corporate OfficeCalifornia | USAAdesto Headquarters1250 Borregas AvenueSunnyvale, CA 94089 Phone: (+1) 408.400.0578Email: [email protected]© 2012

63596N–DFLASH–11/2012AT45DB081DContinuous Array Read, the device will continue reading at the beginning of the next page withno delays incurred during

73596N–DFLASH–11/2012AT45DB081Dduring the page boundary crossover (the crossover from the end of one page to the beginning ofthe next page). When the

83596N–DFLASH–11/2012AT45DB081D7. Program and Erase Commands7.1 Buffer WriteData can be clocked in from the input pin (SI) into either buffer 1 or buf

93596N–DFLASH–11/2012AT45DB081D7.4 Page EraseThe Page Erase command can be used to individually erase any page in the main memory arrayallowing the Bu