Rainbow-electronics MAX105 Bedienungsanleitung

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General Description
The MAX105 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of
in-phase (I) and quadrature (Q) baseband signals. The
MAX105 converts the analog signals of both I and Q
components to digital outputs at 800Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 200MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX105 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.4dB signal-to-noise
plus distortion (SINAD) with a 200MHz analog input sig-
nal and a sampling speed of 800MHz. A fully differen-
tial comparator design and encoding circuits reduce
out-of-sequence errors, and ensure excellent
metastable performance of only one error per 10
16
clock
cycles.
In addition, the MAX105 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX105 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a lower-speed, 400Msps version of the
MAX105, please refer to the MAX107 data sheet.
Applications
VSAT Receivers
WLANs
Test Instrumentation
Communications Systems
Features
Two Matched 6-Bit, 800Msps ADCs
Excellent Dynamic Performance
36.4dB SINAD at f
IN
200MHz and
f
CLK
800MHz
Typical INL and DNL: ±0.25LSB
Channel-to-Channel Phase Matching: ±0.2°
Channel-to-Channel Gain Matching: ±0.04dB
6:12 Demultiplexer reduces the Data Rates to
400MHz
Low Error Rate: 10
16
Metastable States at
800Msps
LVDS Digital Outputs in Two’s Complement
Format
MAX105
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
________________________________________________________________ Maxim Integrated Products 1
REF
I
PRIMARY
PORT
I
AUXILIARY
PORT
Q
PRIMARY
PORT
Q
AUXILIARY
PORT
I ADC
Q ADC
MAX107
Block Diagram
19-2006; Rev 0; 5/01
Ordering Information
PART TEMP. RANGE PIN-PACKAGE
MAX105ECS -40°C to +85°C 80-Pin TQFP-EP
Pin Configuration appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
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Inhaltsverzeichnis

Seite 1 - Wideband Input Amplifier

General DescriptionThe MAX105 is a dual, 6-bit, analog-to-digital converter(ADC) designed to allow fast and precise digitizing ofin-phase (I) and quad

Seite 2

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier10 ______________________________________________________________________________

Seite 3

Detailed DescriptionThe MAX105 is a dual, +5V, 6-bit, 800Msps flash ana-log-to-digital converter (ADC), designed for high-speed, high-bandwidth I&

Seite 4

MAX105signal-to-noise ratio (SNR) specifications will degrade.The MAX105’s on-board, wide-bandwidth input ampli-fiers (I&Q) reduce this effect sig

Seite 5

MAX105 LVDS-outputs provide a typical ±270mV volt-age swing around a common mode voltage of roughly+1.2V, and must be differentially terminated at the

Seite 6

MAX105and are internally buffered with a preamplifier to ensureproper operation of the converter even with small-amplitude sine-wave sources. The MAX1

Seite 7

demultiplexed outputs are presented in dual 6-bit two’scomplement format with two consecutive samples inthe primary and auxiliary output ports on the

Seite 8

MAX105Grounding, Bypassing, and Board LayoutGrounding and power supply decoupling strongly influ-ence the MAX105’s performance. At 800MHz clock fre-qu

Seite 9

plies to the appropriate ground with a 10µF tantalumcapacitor, to filter power supply noise, in parallel with a0.1µF capacitor. A combination of 0.01µ

Seite 10

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier18 ______________________________________________________________________________

Seite 11

clock design limits aperture jitter to typically 1.5psRMS.Figure 11 depicts the aperture jitter (tAJ), which is thesample-to-sample variation in the a

Seite 12

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier2 _______________________________________________________________________________

Seite 13

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier20 ______________________________________________________________________________

Seite 14

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input AmplifierMaxim cannot assume responsibility for use of any circuitry other than circuitry

Seite 15

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier_________________________________________________________________________________

Seite 16

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier4 _______________________________________________________________________________

Seite 17

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier_________________________________________________________________________________

Seite 18

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier6 _______________________________________________________________________________

Seite 19

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier_________________________________________________________________________________

Seite 20

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier8 _______________________________________________________________________________

Seite 21

MAX105Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier_________________________________________________________________________________

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