Rainbow-electronics AT86RF230 Bedienungsanleitung

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ZigBee™/IEEE
802.15.4-
Transceiver
AT86RF230
5131A-ZIGB-06/14/06
Features
Fully Integrated 2.4 GHz-band Transceiver
-101 dBm Receiver Sensitivity
Low Current Consumption (Typical Values)
SLEEP = 0.1 µA
TRX_OFF = 1.7 mA
RX_ON = 16 mA
BUSY_TX = 17 mA (max. P
TX
)
Power Supply Range 1.8V – 3.6V
Internal LDO Voltage Regulators
Battery Monitor
SPI Slave Interface
Baseband Signal Processing Compliant with IEEE 802.15.4
SFD Detection, Spreading/De-spreading, Framing
128-byte FIFO for TRX
Integrated Crystal Oscillator, 16 MHz
Digital RSSI Register, 5-bit Value
Fast Power-up Time < 1 msec
Programmable TX Output Power from -17 dBm up to 3 dBm
Integrated LNA
Low External Component Count
Antenna
Reference Crystal
De-coupling Capacitors
Integrated TX/RX Switch
Integrated PLL Loop Filter
Automatic VCO and Filter Calibration
32-pin Low-profile Lead-free Plastic QFN Package 5 mm x 5 mm x 0.9 mm
Compliant to EN 300 440/328, FCC-CFR-47 Part 15
Compliant to IEEE 802.15.4
Applications
802.15.4 Transceiver
Transceiver for ZigBee System Solutions
Description
The AT86RF230 is a low-power 2.4 GHz transceiver specially designed for low
cost ZigBee/IEEE802.15.4 applications. The AT86RF230 is a true SPI-to-
antenna solution. All RF-critical components except the antenna, crystal and de-
coupling capacitors are integrated on-chip.
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Inhaltsverzeichnis

Seite 1 - Transceiver

ZigBee™/IEEE 802.15.4-Transceiver AT86RF230 5131A-ZIGB-06/14/06 Features • Fully Integrated 2.4 GHz-band Transceiver • -101 dBm Receiver Sensitiv

Seite 2

10 AT86RF230 5131A-ZIGB-06/14/063.9. Crystal Parameter Specifications No Parameter Symbol Min Typ Max Unit Conditions/Notes 3.9.1 Crystal fre

Seite 3

11 AT86RF230 5131A-ZIGB-06/14/064. Basic Operating Modes This section summarizes all features that are needed to provide the basic functionality o

Seite 4

12 AT86RF230 5131A-ZIGB-06/14/06The state change commands FORCE_TRX_OFF and TRX_OFF both lead to a transition into TRX_OFF state. If the transceiver

Seite 5

13 AT86RF230 5131A-ZIGB-06/14/064.2.5. RX_ON and BUSY_RX The RX_ON mode enables the analog and digital receiver blocks and the PLL frequency synth

Seite 6

14 AT86RF230 5131A-ZIGB-06/14/06micro-controller. An additional 256 µs timer ensures that frequency stability is sufficient to drive filter tuning (F

Seite 7

15 AT86RF230 5131A-ZIGB-06/14/064.3.3. State Transition Timing The transition numbers correspond to Figure 4-1 and do not include SPI access time

Seite 8

16 AT86RF230 5131A-ZIGB-06/14/065. Extended Operating Modes The AT86RF230 transceiver implements address filtering, automatic acknowledgement frame

Seite 9

17 AT86RF230 5131A-ZIGB-06/14/062TRX_OFFSLP_TR=1Legend:Blue: SPI Write to Register TRX_STATE (0x02)Red: Control signals via IC PinGreen: Eve

Seite 10 - AT86RF230

18 AT86RF230 5131A-ZIGB-06/14/065.2. Configuration The initialization of the AT86RF230 prior to using RX-AACK or the TX-ARET mode is similar to init

Seite 11 - 4. Basic Operating Modes

19 AT86RF230 5131A-ZIGB-06/14/06even after the maximum number of retries, it will abort the transaction, raise the TRX_END interrupt, and set the v

Seite 12

2 AT86RF230 5131A-ZIGB-06/14/06Table of contents 1. Abbreviations ...

Seite 13 - 4.3.1. Wake-up Procedure

20 AT86RF230 5131A-ZIGB-06/14/066. Functional Description 6.1. RSSI/Energy Detection The internal limiter amplifier provides an RSSI value which re

Seite 14

21 AT86RF230 5131A-ZIGB-06/14/06range from 400 nF to 10 µF. A higher capacitor value provides better voltage stability, but increases the voltage r

Seite 15

22 AT86RF230 5131A-ZIGB-06/14/06The BATMON can be configured using the register 0x11 (BATMON). BATMON_VTH[3:0] sets the threshold voltage. It is prog

Seite 16

23 AT86RF230 5131A-ZIGB-06/14/06CX CX16MHzXTAL1XTAL2VDDCTRIMCTRIMCPARCPARAT86RF230PCBXTAL_TRIM[3:0]XTAL_TRIM[3:0] Figure 6-3. Simplified XOSC Sche

Seite 17

24 AT86RF230 5131A-ZIGB-06/14/06Both calibration routines will be initiated automatically when the PLL is turned on. Additionally, the center frequen

Seite 18 - 5.3.2. TX_ARET_ON

25 AT86RF230 5131A-ZIGB-06/14/067. PHY to Micro-Controller Interface In the following paragraphs, the PHY to micro-controller interface is defined

Seite 19 - 5.3.3. RX_AACK_NOCLK

26 AT86RF230 5131A-ZIGB-06/14/06The interface is designed to work in synchronous or asynchronous mode. In synchronous mode, the CLKM output of the tr

Seite 20

27 AT86RF230 5131A-ZIGB-06/14/06CLKMSELSCLKMOSIMISOCOMMAND WRITE DATA COMMAND XXXX XX XX READ DATAWrite Register Access Read Register Access Figure

Seite 21

28 AT86RF230 5131A-ZIGB-06/14/067.4. Frame Receive Procedure The following transactions are required to receive a frame over the SPI: IRQ issuedread

Seite 22

29 AT86RF230 5131A-ZIGB-06/14/06CLKMSELSCLKMOSIMISOIRQSLP_TRCOMMANDFRAME LENGTH FRAME DATA 1 FRAME DATA 2 FRAME DATA 3 FRAME DATA nXX XX XX XX XX X

Seite 23

3 AT86RF230 5131A-ZIGB-06/14/068. Control Registers ...

Seite 24

30 AT86RF230 5131A-ZIGB-06/14/06CLKMSLP_TRasync timer (controller) elapsed35 main clock cycles Figure 7-12. Sleep and Wake-up Initiated by Asynchron

Seite 25

31 AT86RF230 5131A-ZIGB-06/14/068. Control Registers The AT86RF230 provides a register space of 64 8-bit registers, which is used to configure the

Seite 26 - Bit 7 Bit 6

32 AT86RF230 5131A-ZIGB-06/14/06Reg.-Addr. Register Name Description 0x29 IEEE_ADDR_5 Current node IEEE address for address recognition 0x2A IEE

Seite 27 - XX XX XX READ DATA

33 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:5 TRAC_STATUS 0 R 3’d0: SUCCESS 3’d3: CHANNEL_ACCESS_FAILURE 3’d5:

Seite 28

34 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7 TX_AUTO_CRC_ON 0 R/W AUTO_CRC mode: 1’d0: disable 1’d1: enable 6:4 0

Seite 29 - 5131A-ZIGB-06/14/06

35 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:0 ED_LEVEL 0 R ED level for current channel. The min. ED value (0) indi

Seite 30

36 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:4 CCA_CS_THRES 12 R/W Threshold for CCA_CS 3:0 CCA_ED_THRES 7 R/W An

Seite 31 - 8. Control Registers

37 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 3 DVREG_EXT 0 R/W 1’d0: use internal digital voltage regulator 1’d1: us

Seite 32

38 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:4 XTAL_MODE 15 R/W XTAL Modes: 4’d0: switch off 4’d4: external oscillat

Seite 33

39 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:0 MAN_ID_0 31 R JEDEC manufacturer ID is 32’h 00_00_00_1F for Atmel, bi

Seite 34 - Table 8-6. 0x06 - PHY_RSSI

4 AT86RF230 5131A-ZIGB-06/14/061. Abbreviations AACK — Auto acknowledge ACK — Acknowledge ADC — Analog-to-digital converter AGC — Automatic

Seite 35

40 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:0 IEEE_ADDR_3 0 R/W 8 bits of IEEE address for address recognition, bits[

Seite 36

41 AT86RF230 5131A-ZIGB-06/14/06Bit Field Name Reset R/W Comments 7:6 MIN_BE 3 R/W Minimum back-off exponent in the CSMA/CA algorithm. 5:4

Seite 37

42 AT86RF230 5131A-ZIGB-06/14/069. Application Circuit An application circuit with a single-ended RF connector is shown in Figure 9-1. An SMD-balun

Seite 38

43 AT86RF230 5131A-ZIGB-06/14/06C1C2B187654321910 111213 1415 162526272829303132AT86RF230GNDGNDGNDGNDGNDRFPRFNGNDGNDGNDGNDSLP_TRGNDVDEC1VDEC1XTAL1V

Seite 39

44 AT86RF230 5131A-ZIGB-06/14/0610. Pin Configuration Number Name Type Description 1 GND Ground Analog ground 2 GND Ground Analog ground 3

Seite 40

45 AT86RF230 5131A-ZIGB-06/14/0610.1. Pin-out Diagram GNDGNDGNDRFPRFNGNDGNDIRQMOSIGNDMISOSCLKGNDCLKMGNDGNDGNDVDEC2VDDGNDXTAL2XTAL1GNDGNDSLP_TRGND

Seite 41

46 AT86RF230 5131A-ZIGB-06/14/06LNAPARFPRFNRXTX0.9VTXRXCM FeedbackM0 Figure 10-1. Simplified RF Front-end Schematic A simplified schematic of the RF

Seite 42 - 9. Application Circuit

47 AT86RF230 5131A-ZIGB-06/14/0611. Ordering Information Ordering Code Package Voltage Range Temperature Range AT86RF230-ZU QN 1.8 – 3.6V In

Seite 43

48 AT86RF230 5131A-ZIGB-06/14/0614. Package Drawing – 32QN1 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 32QN1, 32-lead 5.0 x

Seite 44 - 10. Pin Configuration

49 AT86RF230 5131A-ZIGB-06/14/0615. References [1] IEEE Std 802.15.4-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specific

Seite 45

5 AT86RF230 5131A-ZIGB-06/14/062. General Circuit Description LNA PPF ADCAGC PAFrequency SynthesisIQFTNAVREGBATMONSPISlaveInterfaceTX powercont

Seite 46 - 10.5. Digital Pins

5131A-ZIGB-06/14/06Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters

Seite 47 - 12. Soldering Information

6 AT86RF230 5131A-ZIGB-06/14/063. Technical Parameters 3.1. Absolute Maximum Ratings Note: Stresses beyond those listed under “Absolute Maximum Rat

Seite 48

7 AT86RF230 5131A-ZIGB-06/14/06No Parameter Symbol Min Typ Max Unit Conditions/Notes 3.3.5 Controller clock frequency (CLKM) fCLKM 0 1 2

Seite 49 - 16. Revisions

8 AT86RF230 5131A-ZIGB-06/14/06No Parameter Symbol Min Typ Max Unit Conditions/Notes 3.5.7 Spurious emissions 30 – ≤1000 MHz >1 – 12.75 GH

Seite 50 - Atmel Operations

9 AT86RF230 5131A-ZIGB-06/14/063.7. Current Consumption Specifications Test Conditions (unless otherwise stated): Vdd = 3V, Tamb = 25°C, CLKM = OF

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