Rainbow-electronics DS2130Q Bedienungsanleitung

Copyright 1995 by Dallas Semiconductor Corporation.All Rights Reserved. For important information regardingpatents and other intellectual property r

DS2130Q041295 10/22OUTPUT TIME SLOT REGISTER Figure 7(MSB) (LSB)-- D5 D4 D3 D2 D1 D0SYMBOL POSITION NAME AND DESCRIPTION- OTR.7 Reserved; must be zer

DS2130Q041295 11/22DS2130 CONNECTION TO CODEC/FILTER Figure 9FSFSRXMCLKXXRDDVFXI+VFXI–GSXMCLKRVFROVCCGNDAVBB+5V–5VBCLKX+5VMCLKBCLKRSDISCLKDT.0–DT.3DS

DS2130Q041295 12/22PCM AND CPX INPUT/OUTPUTThe organization of the CPX-side input and output timeslots on the DS2130 depends upon the state of bit CX

DS2130Q041295 13/22PCM/CPX I/O (CXS3=1) Figure 11MSB LSB00MSB LSBLSBLSBMSBMSB3–STATE3–STATE3–STATEMSB LSBMSBMSB LSBLSBMSB LSB3–STATECPXOUT CPXOUT C

DS2130Q041295 14/22SPECIAL CLOCK REQUIREMENTSThe minimum number of clock transitions at CPXCLKand PCMCLK is nine per every CPXFS and PCMFS pe-riod (on

DS2130Q041295 15/22ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -1.0V to +7.0VOperating Temperature 0°C to 70°CStorage Temperature -

DS2130Q041295 16/22DTMF RECEIVER CHARACTERISTICS (0°C to 70°C; VCC = +5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESValid Detect Amplitude Range -4

DS2130Q041295 17/22DTMF RECEIVER/GENERATOR TEST CIRCUIT Figure 12+5V–5V+5VMCLKSDISCLKDT.0–DT.3DS2130PCMCLKCPXCLKCPXFSPCMFSCPXINPCMOUTPCMINCPXOUTHost

DS2130Q041295 18/22PCM INTERFACEAC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESPCMCLK, CPXCLK Clock

DS2130Q041295 19/22MASTER CLOCK / RESETAC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC=5V + 10%)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESMCLK Period tP

DS2130Q041295 2/22PIN DESCRIPTION Table 1PIN SYMBOL TYPE DESCRIPTION511915DT0DT1DT2DT3OOOODetect outputs 0-3. These are the four output detect lines

DS2130Q041295 20/22ttttttttttttHOLDHDHFHFSFSDt3–STATE(MSB)(MSB)WH WLPFRCPXCLKPCMCLKCPXFSPCMFSCPXFSPCMFSCPXINPCMINCPXOUTPCMOUTDODZPCM INTERFACE AC TIMI

DS2130Q041295 21/22DS2130 VOICE MESSAGING PROCESSOR 28-PIN DIPA128 1514BDHJFECGK13 EQUAL SPACES AT + .010TNAINCHESDIM MIN MAXA 1.240 1.280B .540 .560C

DS2130Q041295 22/22DS2130Q VOICE MESSAGING PROCESSOR 28-PIN PLCCCH1N1 E E1 D1 D D2 E2e1CA1A2 ABL1B1INCHESDIM MIN MAXA 0.165 0.180A1 0.090 0.120A2 0.

DS2130Q041295 3/22PIN DESCRIPTIONTYPESYMBOL25 PCMFS I PCM side frame sync. An 8 KHz clock signal must be applied for the PCM datainterface. Lower sa

DS2130Q041295 4/22DS2130 SIGNAL FLOW DIAGRAM Figure 1PCMDATAINTERFACEAUDIOCOMPRESSION(Record)AUDIOEXPANSION(Playback)MULTI-TONEGENERATORDTMF HIGH-BAND

DS2130Q041295 5/22HARDWARE RESETRST allows the host to reset the DSP algorithms andthe contents of the serial port control registers. This pinmust b

DS2130Q041295 6/22ADDRESS/COMMAND BYTE Figure 3(MSB) (LSB)-V/T A5 A4 A3 A2 A1 A0SYMBOL POSITION NAME AND DESCRIPTION- ACB.7 Reserved; must be zero fo

DS2130Q041295 7/22VOICE CONTROL REGISTER Figure 4(MSB) (LSB)CP/EXCXS1 CPD1 CXRST CXLB U/A CXS2 CXS3SYMBOL POSITION NAME AND DESCRIPTIONCP/EX VCR.7 C

DS2130Q041295 8/22TONE CONTROL REGISTERThe Tone Control register provides access to the tonegenerator and controls power-down and reset func-tions.The

DS2130Q041295 9/22TONE GENERATION BIT MAPPING1 Table 3TS3-TS0 SIGNAL LEVEL (dBm0)0000 DTMF ‘‘0” -30001 DTMF ‘‘1” -30010 DTMF ‘‘2” -30011 DTMF ‘‘3” -