Rainbow-electronics DS21458 Bedienungsanleitung

1 of 270 REV: 040804 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revision

DS21455/DS21458 Quad T1/E1/J1 Transceivers 10 of 270 The parallel port provides access for control and configuration of all the DS21455/DS21458’s

DS21455/DS21458 Quad T1/E1/J1 Transceivers 100 of 270 17.2 Transmit Signaling Figure 17-2.Simplified Diagram of Transmit Signaling Path

DS21455/DS21458 Quad T1/E1/J1 Transceivers 101 of 270 17.2.1.1 T1 Mode In T1 ESF framing mode, there are four signaling bits per channel (A, B, C,

DS21455/DS21458 Quad T1/E1/J1 Transceivers 102 of 270 Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (E1 Mode, CAS

DS21455/DS21458 Quad T1/E1/J1 Transceivers 103 of 270 Register Name: TS1 to TS16 Register Description: Transmit Signaling Registers (T1 Mode, ESF

DS21455/DS21458 Quad T1/E1/J1 Transceivers 104 of 270 17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS si

DS21455/DS21458 Quad T1/E1/J1 Transceivers 105 of 270 Register Name: SSIE3 Register Description: Software Signaling Insertion Enable 3 Register Ad

DS21455/DS21458 Quad T1/E1/J1 Transceivers 106 of 270 17.2.3 Software Signaling Insertion Enable Registers, T1 Mode In T1 mode, only registers SSI

DS21455/DS21458 Quad T1/E1/J1 Transceivers 107 of 270 17.2.4 Hardware-Based Transmit Signaling In hardware-based mode, signaling data is input via

DS21455/DS21458 Quad T1/E1/J1 Transceivers 108 of 270 18. PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-c

DS21455/DS21458 Quad T1/E1/J1 Transceivers 109 of 270 18.1 Idle Code Programming Examples The following example sets transmit channel 3 idle code

DS21455/DS21458 Quad T1/E1/J1 Transceivers 11 of 270 2. FEATURE HIGHLIGHTS 2.1 General § DS21455: 27mm, 1.27 pitch BGA, compatible replacement

DS21455/DS21458 Quad T1/E1/J1 Transceivers 110 of 270 Register Name: IAAR Register Description: Idle Array Address Register Register Address: 7Eh

DS21455/DS21458 Quad T1/E1/J1 Transceivers 111 of 270 Register Name: TCICE3 Register Description: Transmit Channel Idle Code Enable Register 3 Reg

DS21455/DS21458 Quad T1/E1/J1 Transceivers 112 of 270 Register Name: RCICE3 Register Description: Receive Channel Idle Code Enable Register 3 Regi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 113 of 270 19. CHANNEL BLOCKING REGISTERS The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCB

DS21455/DS21458 Quad T1/E1/J1 Transceivers 114 of 270 Register Name: RCBR3 Register Description: Receive Channel Blocking Register 3 Register Addr

DS21455/DS21458 Quad T1/E1/J1 Transceivers 115 of 270 Register Name: TCBR3 Register Description: Transmit Channel Blocking Register 3 Register Add

DS21455/DS21458 Quad T1/E1/J1 Transceivers 116 of 270 20. ELASTIC STORES OPERATION The DS21455/DS21458 contain dual two-frame, fully independent e

DS21455/DS21458 Quad T1/E1/J1 Transceivers 117 of 270 Register Name: ESCR Register Description: Elastic Store Control Register Register Address: 4

DS21455/DS21458 Quad T1/E1/J1 Transceivers 118 of 270 Register Name: SR5 Register Description: Status Register 5 Register Address: 1Eh Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 119 of 270 20.1 Receive Side See the IOCR1 and IOCR2 registers for information on clock and I/O configur

DS21455/DS21458 Quad T1/E1/J1 Transceivers 12 of 270 2.4 Jitter Attenuator § 32-bit or 128-bit crystal-less jitter attenuator § Requires only a

DS21455/DS21458 Quad T1/E1/J1 Transceivers 120 of 270 20.2 Transmit Side See the IOCR1 and IOCR2 registers for information on clock and I/O configu

DS21455/DS21458 Quad T1/E1/J1 Transceivers 121 of 270 20.4 Minimum-Delay Mode When minimum delay mode is enabled the elastic stores will be forced

DS21455/DS21458 Quad T1/E1/J1 Transceivers 122 of 270 21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21455/DS21458 can implement the G

DS21455/DS21458 Quad T1/E1/J1 Transceivers 123 of 270 22. T1 BIT ORIENTED CODE (BOC) CONTROLLER The DS21455/DS21458 contain a BOC generator on the

DS21455/DS21458 Quad T1/E1/J1 Transceivers 124 of 270 Register Name: BOCC Register Description: BOC Control Register Register Address: 37h Bit #

DS21455/DS21458 Quad T1/E1/J1 Transceivers 125 of 270 Register Name: RFDL (RFDL register bit usage when BOCC.4 = 1) Register Description: Receive

DS21455/DS21458 Quad T1/E1/J1 Transceivers 126 of 270 Register Name: IMR8 Register Description: Interrupt Mask Register 8 Register Address: 25h B

DS21455/DS21458 Quad T1/E1/J1 Transceivers 127 of 270 23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) The DS21455/DS21458, when

DS21455/DS21458 Quad T1/E1/J1 Transceivers 128 of 270 Register Name: RAF Register Description: Receive Align Frame Register Register Address: C6h

DS21455/DS21458 Quad T1/E1/J1 Transceivers 129 of 270 Register Name: TAF Register Description: Transmit Align Frame Register Register Address: D0h

DS21455/DS21458 Quad T1/E1/J1 Transceivers 13 of 270 2.6 System Interface § Dual two-frame, independent receive and transmit elastic stores - In

DS21455/DS21458 Quad T1/E1/J1 Transceivers 130 of 270 23.3 Internal Register Scheme Based On CRC-4 Multiframe (Method 3) On the receive side, ther

DS21455/DS21458 Quad T1/E1/J1 Transceivers 131 of 270 Register Name: RSiNAF Register Description: Receive Si Bits of the Nonalign Frame Register A

DS21455/DS21458 Quad T1/E1/J1 Transceivers 132 of 270 Register Name: RSa4 Register Description: Receive Sa4 Bits Register Address: CBh Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 133 of 270 Register Name: RSa6 Register Description: Receive Sa6 Bits Register Address: CDh Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 134 of 270 Register Name: RSa8 Register Description: Receive Sa8 Bits Register Address: CFh Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 135 of 270 Register Name: TSiAF Register Description: Transmit Si Bits of the Align Frame Register Addr

DS21455/DS21458 Quad T1/E1/J1 Transceivers 136 of 270 Register Name: TSiNAF Register Description: Transmit Si Bits of the Nonalign Frame Register

DS21455/DS21458 Quad T1/E1/J1 Transceivers 137 of 270 Register Name: TSa4 Register Description: Transmit Sa4 Bits Register Address: D5h Bit # 7

DS21455/DS21458 Quad T1/E1/J1 Transceivers 138 of 270 Register Name: TSa6 Register Description: Transmit Sa6 Bits Register Address: D7h Bit # 7

DS21455/DS21458 Quad T1/E1/J1 Transceivers 139 of 270 Register Name: TSa8 Register Description: Transmit Sa8 Bits Register Address: D9h Bit # 7

DS21455/DS21458 Quad T1/E1/J1 Transceivers 14 of 270 2.9 Extended System Information Bus § Host can read interrupt and alarm status on up to eig

DS21455/DS21458 Quad T1/E1/J1 Transceivers 140 of 270 Register Name: TSACR Register Description: Transmit Sa Bit Control Register Register Address

DS21455/DS21458 Quad T1/E1/J1 Transceivers 141 of 270 24. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each

DS21455/DS21458 Quad T1/E1/J1 Transceivers 142 of 270 Table 24-1. HDLC CONTROLLER REGISTERS NAME FUNCTION CONTROL/CONFIGURATION H1TC, HDLC #1 Trans

DS21455/DS21458 Quad T1/E1/J1 Transceivers 143 of 270 24.2 HDLC Configuration Basic configuration of the HDLC controllers is accomplished via the H

DS21455/DS21458 Quad T1/E1/J1 Transceivers 144 of 270 Register Name: H1RC, H2RC Register Description: HDLC #1 Receive Control, HDLC #2 Receive Con

DS21455/DS21458 Quad T1/E1/J1 Transceivers 145 of 270 24.2.1 FIFO Control Control of the transmit and receive FIFOs is accomplished via the FIFO co

DS21455/DS21458 Quad T1/E1/J1 Transceivers 146 of 270 24.3 HDLC Mapping 24.3.1 Receive The HDLC controllers need to be assigned a space in the T1/E

DS21455/DS21458 Quad T1/E1/J1 Transceivers 147 of 270 Register Name: H1RTSBS, H2RTSBS Register Description: HDLC # 1 Receive Time Slot Bits/Sa Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 148 of 270 24.3.2 Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to ch

DS21455/DS21458 Quad T1/E1/J1 Transceivers 149 of 270 Register Name: H1TTSBS, H2TTSBS Register Description: HDLC # 1 Transmit Time Slot Bits/Sa Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 15 of 270 3. BLOCK DIAGRAM Figure 3-1 shows a simplified block diagram highlighting the major compone

DS21455/DS21458 Quad T1/E1/J1 Transceivers 150 of 270 Register Name: SR6, SR7 Register Description: HDLC #1 Status Register 6 HDLC #2 Status Regis

DS21455/DS21458 Quad T1/E1/J1 Transceivers 151 of 270 Register Name: IMR6, IMR7 Register Description: HDLC # 1 Interrupt Mask Register 6 HDLC # 2

DS21455/DS21458 Quad T1/E1/J1 Transceivers 152 of 270 Register Name: INFO5, INFO6 Register Description: HDLC #1 Information Register HDLC #2 Infor

DS21455/DS21458 Quad T1/E1/J1 Transceivers 153 of 270 24.3.3 FIFO Information The transmit FIFO buffer-available register indicates the number of b

DS21455/DS21458 Quad T1/E1/J1 Transceivers 154 of 270 24.3.5 HDLC FIFOS Register Name: H1TF, H2TF Register Description: HDLC # 1 Transmit FIFO, HD

DS21455/DS21458 Quad T1/E1/J1 Transceivers 155 of 270 24.4 Receive HDLC Code Example Below is an example of a receive HDLC routine for controller

DS21455/DS21458 Quad T1/E1/J1 Transceivers 156 of 270 Register Name: RFDL Register Description: Receive FDL Register Register Address: C0h Bit #

DS21455/DS21458 Quad T1/E1/J1 Transceivers 157 of 270 24.5.2 Transmit Section The transmit section will shift out into the T1 data stream, either t

DS21455/DS21458 Quad T1/E1/J1 Transceivers 158 of 270 25. LINE INTERFACE UNIT (LIU) The LIU in the DS21455/DS21458 contains three sections: the re

DS21455/DS21458 Quad T1/E1/J1 Transceivers 159 of 270 Figure 25-2. Basic Unbalanced Network Connections 25.1 LIU Operation T

DS21455/DS21458 Quad T1/E1/J1 Transceivers 16 of 270 Figure 3-2. DS21455 Block Diagram RECEIVEFRAMERRECEIVEBACKPLANEINTERFACETRANSMITBACKPL

DS21455/DS21458 Quad T1/E1/J1 Transceivers 160 of 270 There are two ranges of receive sensitivity for both T1 and E1, which is selectable by the us

DS21455/DS21458 Quad T1/E1/J1 Transceivers 161 of 270 25.3 LIU Transmitter The DS21455/DS21458 use a phase-lock loop along with a precision digital

DS21455/DS21458 Quad T1/E1/J1 Transceivers 162 of 270 25.3.3 Transmit BPV Error Insertion When IBPV (LIC2.5) is transitioned from a zero to a one,

DS21455/DS21458 Quad T1/E1/J1 Transceivers 163 of 270 25.6 CMI (Code Mark Inversion) Option The DS21455/DS21458 provide a CMI interface for connec

DS21455/DS21458 Quad T1/E1/J1 Transceivers 164 of 270 25.7 LIU Control Registers Register Name: LIC1 Register Description: Line Interface Control

DS21455/DS21458 Quad T1/E1/J1 Transceivers 165 of 270 Table 25-2. E1 MODE WITH AUTOMATIC GAIN CONTROL MODE ENABLED (TLBC.6 = 0) APPLICATION LIC1.7

DS21455/DS21458 Quad T1/E1/J1 Transceivers 166 of 270 Register Name: TLBC Register Description: Transmit Line Build-Out Control Register Address:

DS21455/DS21458 Quad T1/E1/J1 Transceivers 167 of 270 Register Name: LIC2 Register Description: Line Interface Control 2 Register Address: 79h Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 168 of 270 Register Name: LIC3 Register Description: Line Interface Control 3 Register Address: 7Ah Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 169 of 270 Register Name: LIC4 Register Description: Line Interface Control 4 Register Address: 7Bh Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 17 of 270 4. DS21455/DS21458 DELTA This section describes the differences between the DS21455 and DS214

DS21455/DS21458 Quad T1/E1/J1 Transceivers 170 of 270 Register Name: INFO2 Register Description: Information Register 2 Register Address: 11h Bit

DS21455/DS21458 Quad T1/E1/J1 Transceivers 171 of 270 Register Name: SR1 Register Description: Status Register 1 Register Address: 16h Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 172 of 270 Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 17h B

DS21455/DS21458 Quad T1/E1/J1 Transceivers 173 of 270 25.8 Recommended Circuits Figure 25-5. Basic Interface NOTES

DS21455/DS21458 Quad T1/E1/J1 Transceivers 174 of 270 Figure 25-6. Protected Interface Using Internal Receive Termination

DS21455/DS21458 Quad T1/E1/J1 Transceivers 175 of 270 25.9 Component Specifications Table 25-6. TRANSFORMER SPECIFICATIONS SPECIFICATION RECOMMEND

DS21455/DS21458 Quad T1/E1/J1 Transceivers 176 of 270 Figure 25-7. E1 Transmit Pulse Template Figure 25-8. T1 Transmit Pul

DS21455/DS21458 Quad T1/E1/J1 Transceivers 177 of 270 Figure 25-9. Jitter Tolerance Figure 25-10. Jitter Attenuation (T1 Mode) FREQUENCY

DS21455/DS21458 Quad T1/E1/J1 Transceivers 178 of 270 Figure 25-11. Jitter Attenuation (E1 Mode) FREQUENCY (Hz)0dB-20dB-40dB-60dB1 10 100 1K 10KJ

DS21455/DS21458 Quad T1/E1/J1 Transceivers 179 of 270 26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS21455/DS21458 can genera

DS21455/DS21458 Quad T1/E1/J1 Transceivers 18 of 270 Figure 4-1. DS21455 Framer/LIU Interim Signals RxLIURxFRAMERTxLIUTxFRAMERMUXMUXRxLIURxFRAME

DS21455/DS21458 Quad T1/E1/J1 Transceivers 180 of 270 Register Name: IBCC Register Description: In-Band Code Control Register Register Address: B6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 181 of 270 Register Name: TCD1 Register Description: Transmit Code Definition Register 1 Register Addre

DS21455/DS21458 Quad T1/E1/J1 Transceivers 182 of 270 Register Name: RUPCD1 Register Description: Receive-Up Code Definition Register 1 Register A

DS21455/DS21458 Quad T1/E1/J1 Transceivers 183 of 270 Register Name: RDNCD1 Register Description: Receive-Down Code Definition Register 1 Register

DS21455/DS21458 Quad T1/E1/J1 Transceivers 184 of 270 Register Name: RDNCD2 Register Description: Receive-Down Code Definition Register 2 Register

DS21455/DS21458 Quad T1/E1/J1 Transceivers 185 of 270 Register Name: RSCD1 Register Description: Receive-Spare Code Definition Register 1 Register

DS21455/DS21458 Quad T1/E1/J1 Transceivers 186 of 270 27. BERT FUNCTION The BERT (Bit Error-Rate Tester) block can generate and detect both pseudor

DS21455/DS21458 Quad T1/E1/J1 Transceivers 187 of 270 27.1 BERT Register Description Register Name: BC1 Register Description: BERT Control Regist

DS21455/DS21458 Quad T1/E1/J1 Transceivers 188 of 270 Register Name: BC2 Register Description: BERT Control Register 2 Register Address: E1h Bit

DS21455/DS21458 Quad T1/E1/J1 Transceivers 189 of 270 Register Name: BIC Register Description: BERT Interface Control Register Register Address: E

DS21455/DS21458 Quad T1/E1/J1 Transceivers 19 of 270 Figure 4-2. DS21458 Framer/LIU Interim Signals RxLIURxFRAMERTxLIUTxFRAMERTPOSO1TNEGO

DS21455/DS21458 Quad T1/E1/J1 Transceivers 190 of 270 Register Name: SR9 Register Description: Status Register 9 Register Address: 26h Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 191 of 270 Register Name: IMR9 Register Description: Interrupt Mask Register 9 Register Address: 27h B

DS21455/DS21458 Quad T1/E1/J1 Transceivers 192 of 270 27.2 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to gen

DS21455/DS21458 Quad T1/E1/J1 Transceivers 193 of 270 27.3 BERT Bit Counter Once the BERT has achieved synchronization, this 32-bit counter will i

DS21455/DS21458 Quad T1/E1/J1 Transceivers 194 of 270 27.4 BERT Error Counter Once the BERT has achieved synchronization, this 24-bit counter will

DS21455/DS21458 Quad T1/E1/J1 Transceivers 195 of 270 28. PAYLOAD ERROR INSERTION FUNCTION An error-insertion function is available in the DS21455

DS21455/DS21458 Quad T1/E1/J1 Transceivers 196 of 270 Register Name: ERC Register Description: Error Rate Control Register Register Address: EBh

DS21455/DS21458 Quad T1/E1/J1 Transceivers 197 of 270 28.1 Number of Error Registers The number of error registers determines how many errors will

DS21455/DS21458 Quad T1/E1/J1 Transceivers 198 of 270 28.1.1 Number of Errors Left Register The host can read the NOELx registers at any time to d

DS21455/DS21458 Quad T1/E1/J1 Transceivers 199 of 270 29. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual frame

DS21455/DS21458 Quad T1/E1/J1 Transceivers 2 of 270 DOCUMENT REVISION HISTORY REVISION CHANGES 040804 New Product Release.

DS21455/DS21458 Quad T1/E1/J1 Transceivers 20 of 270 5. PIN FUNCTION DESCRIPTION 5.1 Transmit Side Pins Signal Name: TCLK Signal Description: T

DS21455/DS21458 Quad T1/E1/J1 Transceivers 200 of 270 Register Name: IBOC Register Description: Interleave Bus Operation Control Register Register

DS21455/DS21458 Quad T1/E1/J1 Transceivers 201 of 270 Figure 29-1. IBO Example RSYSCLK1 TSYSCLK1 RSYNC1 TSSYNC1 RSIG1 TSER1 8.192MHz System

DS21455/DS21458 Quad T1/E1/J1 Transceivers 202 of 270 30. EXTENDED SYSTEM INFORMATION BUS (ESIB) The ESIB function is carried forward from the pre

DS21455/DS21458 Quad T1/E1/J1 Transceivers 203 of 270 Figure 30-1. DS21455 ESIB Group NOTE: UP TO 8 PORTS (TWO DS21455s) CAN BE ARRANGED INTO

DS21455/DS21458 Quad T1/E1/J1 Transceivers 204 of 270 Figure 30-2. DS21458 ESIB Group PORT # 1 ESIBS0ESIBS1ESIBRDPORT # 2 PORT # 3 PORT # 4 DS2

DS21455/DS21458 Quad T1/E1/J1 Transceivers 205 of 270 Register Name: ESIBCR1 Register Description: Extended System Information Bus Control Registe

DS21455/DS21458 Quad T1/E1/J1 Transceivers 206 of 270 Register Name: ESIBCR2 Register Description: Extended System Information Bus Control Registe

DS21455/DS21458 Quad T1/E1/J1 Transceivers 207 of 270 Register Name: ESIB1 Register Description: Extended System Information Bus Register 1 Regist

DS21455/DS21458 Quad T1/E1/J1 Transceivers 208 of 270 31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21455/DS21458 contain an on-chip clock sy

DS21455/DS21458 Quad T1/E1/J1 Transceivers 209 of 270 32. FRACTIONAL T1/E1 SUPPORT The DS21455/DS21458 can be programmed to output gapped clocks f

DS21455/DS21458 Quad T1/E1/J1 Transceivers 21 of 270 Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output A pulse at thi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 210 of 270 33. USER-PROGRAMMABLE OUTPUT PINS The DS21455/DS21458 provide four user-programmable output

DS21455/DS21458 Quad T1/E1/J1 Transceivers 211 of 270 34. TRANSMIT FLOW DIAGRAMS Figure 34-1. T1 Transmit Data Flow ESCR.4 TESETSERTSIGHSIE1-3

DS21455/DS21458 Quad T1/E1/J1 Transceivers 212 of 270 Figure 34-2. T1 Transmit Data Flow (continued) B8ZSEncodingBipolar/NRZcodingT1TCR2.7 B8Z

DS21455/DS21458 Quad T1/E1/J1 Transceivers 213 of 270 Figure 34-3. E1 Transmit Data Flow TSERTSIGHSIE1-4throughPCPRtx_hsig_bufTXESTOREESCR.4

DS21455/DS21458 Quad T1/E1/J1 Transceivers 214 of 270 Figure 34-4. E1 Transmit Data Flow (continued) Per-Channel LoopbackFrom IdleCode MuxRDA

DS21455/DS21458 Quad T1/E1/J1 Transceivers 215 of 270 Figure 34-5. E1 Transmit Data Flow (continued) Bipolar/NRZcodingIOCR1.0 ODFFLBS

DS21455/DS21458 Quad T1/E1/J1 Transceivers 216 of 270 35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT The DS21455/DS21458 IEEE 1149.1 des

DS21455/DS21458 Quad T1/E1/J1 Transceivers 217 of 270 TAP Controller State Machine The TAP controller is a finite state machine that responds to th

DS21455/DS21458 Quad T1/E1/J1 Transceivers 218 of 270 Select-IR-Scan All test registers retain their previous state. The instruction register will

DS21455/DS21458 Quad T1/E1/J1 Transceivers 219 of 270 Figure 35-2. TAP Controller State Diagram 1001111111111110000010000110000SelectDR-ScanCapt

DS21455/DS21458 Quad T1/E1/J1 Transceivers 22 of 270 Signal Name: TNEGI (DS21455 Only) Signal Description: Transmit Negative-Data Input Signal Typ

DS21455/DS21458 Quad T1/E1/J1 Transceivers 220 of 270 35.1 Instruction Register The instruction register contains a shift register as well as a lat

DS21455/DS21458 Quad T1/E1/J1 Transceivers 221 of 270 SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification that support

DS21455/DS21458 Quad T1/E1/J1 Transceivers 222 of 270 35.2 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass registe

DS21455/DS21458 Quad T1/E1/J1 Transceivers 223 of 270 Table 35-4. BOUNDARY SCAN CONTROL BITS CELL # NAME TYPE CONTROL CELL NOTES 0 RCLKO3 observe

DS21455/DS21458 Quad T1/E1/J1 Transceivers 224 of 270 CELL # NAME TYPE CONTROL CELL NOTES 49 TCLKO2 observe_only 50 TPOSO2 observe_only 51 T

DS21455/DS21458 Quad T1/E1/J1 Transceivers 225 of 270 CELL # NAME TYPE CONTROL CELL NOTES 97 TNEGO4 observe_only 98 RCLKO4 observe_only 99 R

DS21455/DS21458 Quad T1/E1/J1 Transceivers 226 of 270 CELL # NAME TYPE CONTROL CELL NOTES 145 TCLKI1 observe_only 146 TCLK1 observe_only 147

DS21455/DS21458 Quad T1/E1/J1 Transceivers 227 of 270 CELL # NAME TYPE CONTROL CELL NOTES 193 RCLK3 observe_only 194 TSIG3 observe_only 195

DS21455/DS21458 Quad T1/E1/J1 Transceivers 228 of 270 36. FUNCTIONAL TIMING DIAGRAMS 36.1 T1 Mode Figure 36-1. Receive Side D4 Timing

DS21455/DS21458 Quad T1/E1/J1 Transceivers 229 of 270 Figure 36-2. Receive Side ESF Timing NOTES: 1) RSYNC in frame mode (IOCR1.4 = 0) and dou

DS21455/DS21458 Quad T1/E1/J1 Transceivers 23 of 270 Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pu

DS21455/DS21458 Quad T1/E1/J1 Transceivers 230 of 270 Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled) NOTES: 1) RCHBLK

DS21455/DS21458 Quad T1/E1/J1 Transceivers 231 of 270 Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) NOTES: 1)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 232 of 270 Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) NOTES: 1)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 233 of 270 Figure 36-6. Transmit Side D4 Timing NOTES: 1) TSYNC in the frame mode (IOCR1.2 = 0) and

DS21455/DS21458 Quad T1/E1/J1 Transceivers 234 of 270 Figure 36-7. Transmit Side ESF Timing NOTES: 1) TSYNC in frame mode (IOCR1.2 = 0) and do

DS21455/DS21458 Quad T1/E1/J1 Transceivers 235 of 270 Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled) NOTES: 1) TSYN

DS21455/DS21458 Quad T1/E1/J1 Transceivers 236 of 270 Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) NOTE: 1)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 237 of 270 Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) NOTES:

DS21455/DS21458 Quad T1/E1/J1 Transceivers 238 of 270 36.2 E1 Mode Figure 36-11. Receive Side Timing NOTES: 1) RSYNC in frame mode (IOCR1.5 =

DS21455/DS21458 Quad T1/E1/J1 Transceivers 239 of 270 Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled) NOTES: 1) RCHBLK

DS21455/DS21458 Quad T1/E1/J1 Transceivers 24 of 270 Signal Name: BPCLK Signal Description: Backplane Clock Signal Type: Output A user-selectable

DS21455/DS21458 Quad T1/E1/J1 Transceivers 240 of 270 Figure 36-13. Receive Side Boundary Timing, RSYSCLK = 1.544MHz (With Elastic Store Enabled)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 241 of 270 Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz (With Elastic Store Enabled)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 242 of 270 Figure 36-15. Receive IBO Channel Interleave Mode Timing NOTES: 1) 4.096MHz bus configu

DS21455/DS21458 Quad T1/E1/J1 Transceivers 243 of 270 Figure 36-16. Receive IBO Frame Interleave Mode Timing NOTES: 1) 4.096MHz bus configurat

DS21455/DS21458 Quad T1/E1/J1 Transceivers 244 of 270 Figure 36-17. G.802 Timing, E1 Mode Only NOTE: 1) RCHBLK or TCHBLK programmed to pulse

DS21455/DS21458 Quad T1/E1/J1 Transceivers 245 of 270 Figure 36-18. Transmit Side Timing NOTES: 1) TSYNC in frame mode (IOCR1.2 = 0). 2) TSYN

DS21455/DS21458 Quad T1/E1/J1 Transceivers 246 of 270 Figure 36-19. Transmit Side Boundary Timing (With Elastic Store Disabled) NOTES: 1) TSY

DS21455/DS21458 Quad T1/E1/J1 Transceivers 247 of 270 Figure 36-20. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz (With Elastic Store Enabled)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 248 of 270 Figure 36-21. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz (With Elastic Store Enabled)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 249 of 270 Figure 36-22. Transmit IBO Channel Interleave Mode Timing NOTES: 1) 4.096MHz bus configu

DS21455/DS21458 Quad T1/E1/J1 Transceivers 25 of 270 Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmu

DS21455/DS21458 Quad T1/E1/J1 Transceivers 250 of 270 Figure 36-23. Transmit IBO Frame Interleave Mode Timing NOTES: 1) 4.096MHz bus configura

DS21455/DS21458 Quad T1/E1/J1 Transceivers 251 of 270 37. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Groun

DS21455/DS21458 Quad T1/E1/J1 Transceivers 252 of 270 RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C for DS21455/DS21458; TA = -40°C to +85

DS21455/DS21458 Quad T1/E1/J1 Transceivers 253 of 270 38. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals, 20pF f

DS21455/DS21458 Quad T1/E1/J1 Transceivers 254 of 270 Figure 38-1. Intel Bus Read Timing (BTS = 0 / MUX = 1) Figure 38-2. Intel Bus Write Tim

DS21455/DS21458 Quad T1/E1/J1 Transceivers 255 of 270 Figure 38-3. Motorola Bus Timing (BTS = 1 / MUX = 1) tASDASHPWttASLAHLtCStASLtttDSWDHWtCHttt

DS21455/DS21458 Quad T1/E1/J1 Transceivers 256 of 270 38.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS–NONMULTIPLEXED PARALLEL PORT (

DS21455/DS21458 Quad T1/E1/J1 Transceivers 257 of 270 Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0) Figure 38-5. Intel Bus Write Tim

DS21455/DS21458 Quad T1/E1/J1 Transceivers 258 of 270 Figure 38-6. Motorola Bus Read Timing (BTS = 1 / MUX = 0) Figure 38-7.

DS21455/DS21458 Quad T1/E1/J1 Transceivers 259 of 270 38.3 Receive Side AC Characteristics AC CHARACTERISTICS–RECEIVE SIDE (VDD = 3.3V ±5%, TA =

DS21455/DS21458 Quad T1/E1/J1 Transceivers 26 of 270 Signal Name: CS (DS21458 Only) Signal Description: Chip Select Signal Type: Input Must be low

DS21455/DS21458 Quad T1/E1/J1 Transceivers 260 of 270 AC CHARACTERISTICS–RECEIVE SIDE (continued) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21455/DS

DS21455/DS21458 Quad T1/E1/J1 Transceivers 261 of 270 Figure 38-9. Receive Side Timing, Elastic Store Disabled (E1 Mode) tD11tD2tD2tD2tD2RSER / R

DS21455/DS21458 Quad T1/E1/J1 Transceivers 262 of 270 Figure 38-10. Receive Side Timing, Elastic Store Enabled (T1 Mode) FttRtD3tD4tD4tD4ttSUHDR

DS21455/DS21458 Quad T1/E1/J1 Transceivers 263 of 270 Figure 38-11. Receive Side Timing, Elastic Store Enabled (E1 Mode) tFtRtD31tD4tD4tD4ttSUHD2R

DS21455/DS21458 Quad T1/E1/J1 Transceivers 264 of 270 Figure 38-12. Receive Line Interface Timing tFtRRPOSI, RNEGIRCLKICLttCPCHttSUtHDtDDRPOSO,

DS21455/DS21458 Quad T1/E1/J1 Transceivers 265 of 270 38.4 Transmit AC Characteristics AC CHARACTERISTICS–TRANSMIT SIDE (VDD = 3.3V ±5%, TA = 0°C

DS21455/DS21458 Quad T1/E1/J1 Transceivers 266 of 270 Figure 38-13. Transmit Side Timing 4) TCHCLK and TCHBLK are synchronous with TCLK when the

DS21455/DS21458 Quad T1/E1/J1 Transceivers 267 of 270 Figure 38-14. Transmit Side Timing, Elastic Store Enabled NOTES: 1) TSER is only sampled

DS21455/DS21458 Quad T1/E1/J1 Transceivers 268 of 270 Figure 38-15. Transmit Line Interface Timing TCLKOTPOSO, TNEGOtDDtFtRTCLKITPOSI, TNEGIttLL

DS21455/DS21458 Quad T1/E1/J1 Transceivers 269 of 270 39. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most c

DS21455/DS21458 Quad T1/E1/J1 Transceivers 27 of 270 Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This

DS21455/DS21458 Quad T1/E1/J1 Transceivers 270 of 270 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than c

DS21455/DS21458 Quad T1/E1/J1 Transceivers 28 of 270 5.7 Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Su

DS21455/DS21458 Quad T1/E1/J1 Transceivers 29 of 270 5.8 Pin Descriptions Table 5-1. DS21455 PIN DESCRIPTION PIN NAME TYPE FUNCTION U3 A0 I

DS21455/DS21458 Quad T1/E1/J1 Transceivers 3 of 270 TABLE OF CONTENTS 1. DESCRIPTION ...

DS21455/DS21458 Quad T1/E1/J1 Transceivers 30 of 270 PIN NAME TYPE FUNCTION B7 DVSS — Digital Signal Ground B9 DVSS — Digital Signal Ground H20

DS21455/DS21458 Quad T1/E1/J1 Transceivers 31 of 270 PIN NAME TYPE FUNCTION A12 RLCLK2 O Receive Link Clock for Transceiver 2 D3 RLCLK3 O Re

DS21455/DS21458 Quad T1/E1/J1 Transceivers 32 of 270 PIN NAME TYPE FUNCTION G3 RSYSCLK3 I Receive System Clock for Transceiver 3 W14 RSYSCLK4

DS21455/DS21458 Quad T1/E1/J1 Transceivers 33 of 270 PIN NAME TYPE FUNCTION N20 TNEGO4 O Transmit Negative-Data Output from Framer on Transceiv

DS21455/DS21458 Quad T1/E1/J1 Transceivers 34 of 270 Table 5-2. DS21458 PIN DESCRIPTION PIN NAME TYPE FUNCTION H2 A0 I Address Bus Bit 0 (Lsb)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 35 of 270 PIN NAME TYPE FUNCTION J9 ESIBS1 I/O Extended System Information Bus 1 H5 INT O Interrupt

DS21455/DS21458 Quad T1/E1/J1 Transceivers 36 of 270 PIN NAME TYPE FUNCTION J2 RNEGO1 O Receive Negative Data from the LIU on Transceiver 1 H11

DS21455/DS21458 Quad T1/E1/J1 Transceivers 37 of 270 PIN NAME TYPE FUNCTION N2 TCHBLK1 O Transmit Channel Block for Transceiver 1 E13 TCHBLK2

DS21455/DS21458 Quad T1/E1/J1 Transceivers 38 of 270 PIN NAME TYPE FUNCTION N16 TRING4 O Transmit Analog Ring Output for Transceiver 4 M6 TSER

DS21455/DS21458 Quad T1/E1/J1 Transceivers 39 of 270 5.9 Packages The package diagrams below show the lead pattern that will be placed on the targ

DS21455/DS21458 Quad T1/E1/J1 Transceivers 4 of 270 13. I/O PIN CONFIGURATION OPTIONS...

DS21455/DS21458 Quad T1/E1/J1 Transceivers 40 of 270 Figure 5-2. DS21458 Pin Diagram, 17mm CSBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A TNEG0

DS21455/DS21458 Quad T1/E1/J1 Transceivers 41 of 270 6. PARALLEL PORT The transceiver is controlled via either a nonmultiplexed (MUX = 0) or a mult

DS21455/DS21458 Quad T1/E1/J1 Transceivers 42 of 270 ADDRESS REGISTER NAME REGISTER ABBREVIATION PAGE 2A Per-Channel Data Register 2 PCDR2 47 2B

DS21455/DS21458 Quad T1/E1/J1 Transceivers 43 of 270 ADDRESS REGISTER NAME REGISTER ABBREVIATION PAGE 5F Transmit Signaling Register 16 TS16 102

DS21455/DS21458 Quad T1/E1/J1 Transceivers 44 of 270 ADDRESS REGISTER NAME REGISTER ABBREVIATION PAGE 94 HDLC #1 Receive Channel Select 3 H1RCS3

DS21455/DS21458 Quad T1/E1/J1 Transceivers 45 of 270 ADDRESS REGISTER NAME REGISTER ABBREVIATION PAGE C9 Receive Si Nonalign Frame RSiNAF 131 CA

DS21455/DS21458 Quad T1/E1/J1 Transceivers 46 of 270 7. SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet th

DS21455/DS21458 Quad T1/E1/J1 Transceivers 47 of 270 Register Name: PCDR1 Register Description: Per-Channel Data Register 1 Register Address: 29h

DS21455/DS21458 Quad T1/E1/J1 Transceivers 48 of 270 8. PROGRAMMING MODEL The DS21455/DS21458 register map is divided into three groups: T1 specifi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 49 of 270 8.1 Power-Up Sequence The DS21455/DS21458 contain an on-chip power-up reset function, which

DS21455/DS21458 Quad T1/E1/J1 Transceivers 5 of 270 24.5.1 Receive Section ...

DS21455/DS21458 Quad T1/E1/J1 Transceivers 50 of 270 8.2 Interrupt Handling Various alarms, conditions, and events in the DS21455/DS21458 can cause

DS21455/DS21458 Quad T1/E1/J1 Transceivers 51 of 270 8.4 Information Registers Information registers operate the same as status registers except t

DS21455/DS21458 Quad T1/E1/J1 Transceivers 52 of 270 9. CLOCK MAP Figure 9-1 shows the clock map of the DS21455/DS21458. The routing for the transm

DS21455/DS21458 Quad T1/E1/J1 Transceivers 53 of 270 10. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21455/DS21458 is con

DS21455/DS21458 Quad T1/E1/J1 Transceivers 54 of 270 Register Name: T1RCR2 Register Description: T1 Receive Control Register 2 Register Address: 0

DS21455/DS21458 Quad T1/E1/J1 Transceivers 55 of 270 Register Name: T1TCR1 Register Description: T1 Transmit Control Register 1 Register Address:

DS21455/DS21458 Quad T1/E1/J1 Transceivers 56 of 270 Register Name: T1TCR2 Register Description: T1 Transmit Control Register 2 Register Address:

DS21455/DS21458 Quad T1/E1/J1 Transceivers 57 of 270 Register Name: T1CCR1 Register Description: T1 Common Control Register 1 Register Address: 07

DS21455/DS21458 Quad T1/E1/J1 Transceivers 58 of 270 10.2 T1 Transmit Transparency The software-signaling insertion-enable registers, SSIE1–SSIE4

DS21455/DS21458 Quad T1/E1/J1 Transceivers 59 of 270 10.3 AIS-CI and RAI-CI Generation and Detection The DS21455/DS21458 can transmit and detect

DS21455/DS21458 Quad T1/E1/J1 Transceivers 6 of 270 LIST OF FIGURES Figure 3-1. DS21458 Block Diagram...

DS21455/DS21458 Quad T1/E1/J1 Transceivers 60 of 270 10.4 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code g

DS21455/DS21458 Quad T1/E1/J1 Transceivers 61 of 270 Register Name: T1RDMR1 Register Description: T1 Receive Digital-Milliwatt Enable Register 1 R

DS21455/DS21458 Quad T1/E1/J1 Transceivers 62 of 270 10.5 T1 Information Register Register Name: INFO1 Register Description: Information Register

DS21455/DS21458 Quad T1/E1/J1 Transceivers 63 of 270 Table 10-1. T1 ALARM CRITERIA ALARM SET CRITERIA CLEAR CRITERIA Blue Alarm (AIS) (Note 1)

DS21455/DS21458 Quad T1/E1/J1 Transceivers 64 of 270 11. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21455/DS21458 is con

DS21455/DS21458 Quad T1/E1/J1 Transceivers 65 of 270 Table 11-1. E1 SYNC/RESYNC CRITERIA FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA

DS21455/DS21458 Quad T1/E1/J1 Transceivers 66 of 270 Register Name: E1TCR1 Register Description: E1 Transmit Control Register 1 Register Address:

DS21455/DS21458 Quad T1/E1/J1 Transceivers 67 of 270 Register Name: E1TCR2 Register Description: E1 Transmit Control Register 2 Register Address:

DS21455/DS21458 Quad T1/E1/J1 Transceivers 68 of 270 11.2 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or

DS21455/DS21458 Quad T1/E1/J1 Transceivers 69 of 270 11.3 E1 Information Registers Register Name: INFO3 Register Description: Information Regist

DS21455/DS21458 Quad T1/E1/J1 Transceivers 7 of 270 Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) ...

DS21455/DS21458 Quad T1/E1/J1 Transceivers 70 of 270 Table 11-3. E1 ALARM CRITERIA ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. RLOS An RLOS cond

DS21455/DS21458 Quad T1/E1/J1 Transceivers 71 of 270 12. COMMON CONTROL AND STATUS REGISTERS Register Name: CCR1 Register Description: Common Con

DS21455/DS21458 Quad T1/E1/J1 Transceivers 72 of 270 Register Name: IDR Register Description: Device Identification Register Register Address: 0Fh

DS21455/DS21458 Quad T1/E1/J1 Transceivers 73 of 270 Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19h Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 74 of 270 Register Name: SR3 Register Description: Status Register 3 Register Address: 1Ah Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 75 of 270 Register Name: IMR3 Register Description: Interrupt Mask Register 3 Register Address: 1Bh Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 76 of 270 Register Name: SR4 Register Description: Status Register 4 Register Address: 1Ch Bit # 7 6

DS21455/DS21458 Quad T1/E1/J1 Transceivers 77 of 270 Register Name: IMR4 Register Description: Interrupt Mask Register 4 Register Address: 1Dh Bi

DS21455/DS21458 Quad T1/E1/J1 Transceivers 78 of 270 13. I/O PIN CONFIGURATION OPTIONS Register Name: IOCR1 Register Description: I/O Configurati

DS21455/DS21458 Quad T1/E1/J1 Transceivers 79 of 270 Register Name: IOCR2 Register Description: I/O Configuration Register 2 Register Address: 02h

DS21455/DS21458 Quad T1/E1/J1 Transceivers 8 of 270 LIST OF TABLES Table 5-1. DS21455 PIN DESCRIPTION...

DS21455/DS21458 Quad T1/E1/J1 Transceivers 80 of 270 FRAMER LOOPBACKRECEIVELIUTRANSMITLIUJITTERATTENUATORJITTERATTENUATORRECEIVEFRAMERTRANSMITFRAME

DS21455/DS21458 Quad T1/E1/J1 Transceivers 81 of 270 PAYLOAD LOOPBACK (CAN BE DONE ON A PER-CHANNEL BASIS)RECEIVELIUTRANSMITLIUJITTERATTENUATORJITT

DS21455/DS21458 Quad T1/E1/J1 Transceivers 82 of 270 Bit 3/Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal t

DS21455/DS21458 Quad T1/E1/J1 Transceivers 83 of 270 14.1 Per-Channel Payload Loopback The per-channel loopback registers (PCLRs) determine whic

DS21455/DS21458 Quad T1/E1/J1 Transceivers 84 of 270 Register Name: PCLR3 Register Description: Per-Channel Loopback Enable Register 3 Register Ad

DS21455/DS21458 Quad T1/E1/J1 Transceivers 85 of 270 15. ERROR COUNT REGISTERS The DS21455/DS21458 contain four counters that are used to accumul

DS21455/DS21458 Quad T1/E1/J1 Transceivers 86 of 270 15.1 Line Code Violation Count Register (LCVCR) 15.1.1 T1 Operation T1 code violations are

DS21455/DS21458 Quad T1/E1/J1 Transceivers 87 of 270 Register Name: LCVCR1 Register Description: Line Code Violation Count Register 1 Register Add

DS21455/DS21458 Quad T1/E1/J1 Transceivers 88 of 270 15.2 Path Code Violation Count Register (PCVCR) 15.2.1 T1 Operation The path code violation

DS21455/DS21458 Quad T1/E1/J1 Transceivers 89 of 270 15.3 Frames Out Of Sync Count Register (FOSCR) 15.3.1 T1 Operation The FOSCR is used to coun

DS21455/DS21458 Quad T1/E1/J1 Transceivers 9 of 270 1. DESCRIPTION The DS21455 and DS21458 are quad monolithic devices featuring independent trans

DS21455/DS21458 Quad T1/E1/J1 Transceivers 90 of 270 Register Name: FOSCR1 Register Description: Frames Out Of Sync Count Register 1 Register Addr

DS21455/DS21458 Quad T1/E1/J1 Transceivers 91 of 270 16. DS0 MONITORING FUNCTION The DS21455/DS21458 can monitor one DS0 64kbps channel in the tr

DS21455/DS21458 Quad T1/E1/J1 Transceivers 92 of 270 16.2 Receive DS0 Monitor Registers Register Name: RDS0SEL Register Description: Receive Chan

DS21455/DS21458 Quad T1/E1/J1 Transceivers 93 of 270 17. SIGNALING OPERATION There are two methods to access receive signaling data and provide tra

DS21455/DS21458 Quad T1/E1/J1 Transceivers 94 of 270 17.1.1 Processor-Based Receive Signaling The robbed-bit signaling (T1) or TS16 CAS signaling

DS21455/DS21458 Quad T1/E1/J1 Transceivers 95 of 270 17.1.2.2 Force Receive Signaling All Ones In T1 mode, the user can, on a per-channel basis, f

DS21455/DS21458 Quad T1/E1/J1 Transceivers 96 of 270 Register Name: SIGCR Register Description: Signaling Control Register Register Address: 40h

DS21455/DS21458 Quad T1/E1/J1 Transceivers 97 of 270 Register Name: RS1 to RS12 Register Description: Receive Signaling Registers (T1 Mode, ESF Fo

DS21455/DS21458 Quad T1/E1/J1 Transceivers 98 of 270 Register Name: RS1 to RS16 Register Description: Receive Signaling Registers (E1 Mode, CAS Fo

DS21455/DS21458 Quad T1/E1/J1 Transceivers 99 of 270 Register Name: RSCSE1, RSCSE2, RSCSE3, RSCSE4 Register Description: Receive Signaling Change