Rainbow-electronics DS21458 Bedienungsanleitung Seite 239
- Seite / 270
- Inhaltsverzeichnis
- LESEZEICHEN
- DS21455/DS21458 1
- Quad T1/E1/J1 Transceivers 1
- DOCUMENT REVISION HISTORY 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 6
- LIST OF TABLES 8
- 1. DESCRIPTION 9
- 1.1 Standards 10
- 2. FEATURE HIGHLIGHTS 11
- 2.1 General 11
- 2.2 Line Interface 11
- 2.3 Clock Synthesizer 11
- 2.4 Jitter Attenuator 12
- 2.5 Framer/Formatter 12
- 2.6 System Interface 13
- 2.7 HDLC Controllers 13
- 2.8 Test and Diagnostics 13
- 2.10 Control Port 14
- DS21458 15
- 4. DS21455/DS21458 DELTA 17
- 4.1 Package 17
- 4.2 Controller Interface 17
- 4.3 ESIB Function 17
- 18 of 270 18
- 5. PIN FUNCTION DESCRIPTION 20
- 5.1 Transmit Side Pins 20
- 5.2 Receive Side Pins 22
- CS (DS21458 Only) 26
- CS is an active-low signal 26
- WR (R/W) 26
- WR is an active-low signal 26
- 5.6 Line Interface Pins 27
- 5.7 Supply Pins 28
- 5.8 Pin Descriptions 29
- RD (DS) 30
- 5.9 Packages 39
- 6. PARALLEL PORT 41
- 6.1 Register Map 41
- 8. PROGRAMMING MODEL 48
- 8.1 Power-Up Sequence 49
- 8.2 Interrupt Handling 50
- Status Registers 50
- 8.4 Information Registers 51
- 9. CLOCK MAP 52
- Figure 9-1. Clock Map 52
- 10.1 T1 Control Registers 53
- 58 of 270 58
- 60 of 270 60
- 11.1 E1 Control Registers 64
- 70 of 270 70
- 14. LOOPBACK CONFIGURATIONS 80
- Table 14-1. LIUC CONTROL 82
- 15. ERROR COUNT REGISTERS 85
- 17. SIGNALING OPERATION 93
- 17.1 Receive Signaling 93
- 94 of 270 94
- 95 of 270 95
- 17.2 Transmit Signaling 100
- 107 of 270 107
- 116 of 270 116
- 20.1 Receive Side 119
- 20.2 Transmit Side 120
- 20.4 Minimum-Delay Mode 121
- NEW Sa BIT 122
- TPOSO/TNEGO 122
- 22.1 Transmit BOC 123
- 22.2 Receive BOC 123
- 127 of 270 127
- 24. HDLC CONTROLLERS 141
- 24.2 HDLC Configuration 143
- 24.3 HDLC Mapping 146
- 24.3.5 HDLC FIFOS 154
- 155 of 270 155
- Bit # 7 6 5 4 3 2 1 0 156
- Default 0 0 0 0 0 0 0 0 156
- 24.6 D4/SLC-96 Operation 157
- 25.1 LIU Operation 159
- 25.2 LIU Receiver 159
- 25.3 LIU Transmitter 161
- 25.4 MCLK Prescaler 162
- 25.5 Jitter Attenuator 162
- Figure 25-4. CMI Coding 163
- 25.7 LIU Control Registers 164
- Table 25-1. TPD CONTROL 164
- **N.M. = not meaningful 165
- 3) C = 1µF ceramic 173
- DS21455/458 174
- 175 of 270 175
- Template 176
- DS21458/455 177
- DETECTION 179
- 27. BERT FUNCTION 186
- 27.3 BERT Bit Counter 193
- 27.4 BERT Error Counter 194
- 195 of 270 195
- 29.1 Channel Interleave Mode 199
- 29.2 Frame Interleave Mode 199
- Figure 29-1. IBO Example 201
- 202 of 270 202
- T1 TRANSMIT 211
- TPOS TNEG 212
- E1 TRANSMIT 213
- TEST ACCESS PORT 216
- CONTROLLER 216
- 35.1 Instruction Register 220
- Table 35-3. DEVICE ID CODES 221
- 35.2 Test Registers 222
- 35.3 Boundary Scan Register 222
- 35.4 Bypass Register 222
- 35.5 Identification Register 222
- WR (R/W) observe_only 223
- RD (DS) observe_only 223
- CS2/A9 observe_only 224
- 36.1 T1 Mode 228
- Enabled) 231
- LSB F MSB LSB MSB LSB MSB 235
- ABC/AD/B ABC/AD/B 235
- CHANNEL 1CHANNEL 24 236
- CHANNEL 23 236
- CHANNEL 1CHANNEL 32 237
- CHANNEL 31 237
- 239 of 270 239
- LSB FMSB 240
- BIT DETAIL 242
- LSB MSB LSB MSB 246
- DON'T CARE 246
- A8 & A9 255
- Bit Position 261
- Channel 1 261
- Sa4 to Sa8 261
- 39. PACKAGE INFORMATION 269
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