Rainbow-electronics DS31256 Bedienungsanleitung Seite 172
- Seite / 181
- Inhaltsverzeichnis
- LESEZEICHEN
- DS31256 Envoy 1
- 256-Channel, High-Throughput 1
- HDLC Controlle 1
- TABLE OF CONTENTS 2
- 3 of 181 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. MAIN FEATURES 6
- 2. DETAILED DESCRIPTION 7
- 8 of 181 8
- 9 of 181 9
- Figure 2-1. Block Diagram 10
- 11 of 181 11
- 12 of 181 12
- 3. SIGNAL DESCRIPTION 13
- 3.1 Overview/Signal List 13
- Signal Naming Convention 13
- Table 3-B. RS Sampled Edge 18
- Table 3-C. TS Sampled Edge 19
- 20 of 181 20
- 3.4 JTAG Signal Description 21
- 22 of 181 22
- 23 of 181 23
- 24 of 181 24
- 3.6 PCI Extension Signals 25
- 4. MEMORY MAP 26
- 4.1 Introduction 26
- 27 of 181 27
- 28 of 181 28
- 4.6 HDLC Registers (4xx) 29
- 4.7 BERT Registers (5xx) 29
- 4.10 FIFO Registers (9xx) 30
- 31 of 181 31
- 32 of 181 32
- 33 of 181 33
- 5.3 Status and Interrupt 34
- 35 of 181 35
- SM: Status Master Register 36
- SV54: Status for V54 Detector 36
- n/a n/a n/a n/a n/a 37
- 0 0 0 0 0 0 39
- 0 0 0 0 0 0 0 39
- at the PCI bus 40
- 41 of 181 41
- 0 = interrupt masked 42
- 43 of 181 43
- 6. LAYER 1 44
- 6.1 General Description 44
- 45 of 181 45
- 46 of 181 46
- 47 of 181 47
- 48 of 181 48
- 49 of 181 49
- 50 of 181 50
- 51 of 181 51
- 54
- 55 of 181 55
- 6.4 Receive V.54 Detector 56
- 57 of 181 57
- 58 of 181 58
- 59 of 181 59
- 6.5 BERT 60
- Figure 6-7. BERT Mux Diagram 60
- n/a n/a TC 61
- 62 of 181 62
- n/a TC 63
- 64 of 181 64
- 65 of 181 65
- 66 of 181 66
- 7. HDLC 67
- 7.1 General Description 67
- 68 of 181 68
- 69 of 181 69
- 70 of 181 70
- 72 of 181 72
- 73 of 181 73
- 8. FIFO 74
- Figure 8-1. FIFO Example 75
- 8.1.1 Receive High Watermark 76
- 8.1.2 Transmit Low Watermark 76
- 77 of 181 77
- 80 of 181 80
- 82 of 181 82
- 9.1 Introduction 83
- 84 of 181 84
- 9.2 Receive Side 85
- 9.2.1 Overview 85
- 86 of 181 86
- 87 of 181 87
- 88 of 181 88
- 89 of 181 89
- 9.2.2 Packet Descriptors 90
- 91 of 181 91
- 9.2.3 Free Queue 92
- Calculation 93
- 95 of 181 95
- 96 of 181 96
- 9.2.4 Done Queue 97
- 98 of 181 98
- 99 of 181 99
- DS31256 100
- 100 of 181 100
- 101 of 181 101
- 102 of 181 102
- 103 of 181 103
- 104 of 181 104
- 9.3 Transmit Side 105
- 9.3.1 Overview 105
- 106 of 181 106
- 107 of 181 107
- 108 of 181 108
- 109 of 181 109
- 110 of 181 110
- 111 of 181 111
- 112 of 181 112
- 113 of 181 113
- 9.3.2 Packet Descriptors 114
- 115 of 181 115
- 9.3.3 Pending Queue 116
- 117 of 181 117
- 118 of 181 118
- 119 of 181 119
- 9.3.4 Done Queue 120
- 121 of 181 121
- 122 of 181 122
- 123 of 181 123
- 124 of 181 124
- 9.3.5 DMA Configuration RAM 125
- 126 of 181 126
- 127 of 181 127
- 128 of 181 128
- 129 of 181 129
- 10. PCI BUS 130
- 10.1.1 PCI Read Cycle 131
- Figure 10-2. PCI Bus Read 131
- 10.1.2 PCI Write Cycle 132
- Figure 10-3. PCI Bus Write 132
- 10.1.3 PCI Bus Arbitration 133
- 10.1.4 PCI Initiator Abort 133
- 10.1.5 PCI Target Retry 134
- 10.1.7 PCI Target Abort 135
- 136 of 181 136
- 137 of 181 137
- 10.2.1 Command Bits (PCMD0) 138
- 10.2.2 Status Bits (PCMD0) 139
- 140 of 181 140
- 141 of 181 141
- 142 of 181 142
- 10.2.3 Command Bits (PCMD1) 143
- 10.2.4 Status Bits (PCMD1) 144
- Register Name: PLTH1 145
- 146 of 181 146
- 11. LOCAL BUS 147
- 11.1 General Description 147
- 11.1.1 PCI Bridge Mode 149
- LBHE Setting 150
- 11.1.2 Configuration Mode 151
- 152 of 181 152
- 153 of 181 153
- 154 of 181 154
- 156 of 181 156
- Intel Mode (LIM = 0) 157
- 159 of 181 159
- 160 of 181 160
- Motorola Mode (LIM = 1) 161
- 12. JTAG 163
- 12.1 JTAG Description 163
- Figure 12-1. Block Diagram 163
- 164 of 181 164
- 165 of 181 165
- 166 of 181 166
- 12.4 Test Registers 167
- 13. AC CHARACTERISTICS 168
- ABSOLUTE MAXIMUM RATINGS 168
- DC CHARACTERISTICS 168
- 172 of 181 172
- (continued) 173
- 14. MECHANICAL DIMENSIONS 176
- 14.1 256 PBGA Package 176
- 15. APPLICATIONS 177
- 179 of 181 179
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