Rainbow-electronics DS3134 Bedienungsanleitung

1 of 203 101600FEATURES• 256 Channel HDLC Controller that Supportsup to 64 T1 or E1 Lines or Two T3 Lines• 256 Independent bi-directional HDLCchanne

DS313410 of 203DATA SHEET DEFINITIONS Table 1BAcronymOr Term DefinitionBERT Bit Error Rate Tester.Descriptor A message passed back and forth between

DS3134100 of 203Receive DMA ActionsA typical scenario for the Receive DMA is as follows:1. The receive DMA gets a request from the Receive FIFO that

DS3134101 of 203Receive DMA Operation Figure 8.1.1AFree Data Buffer Address00h08h10hFree Queue Descriptors(circular queue)00h04h08hDone Queue Descri

DS3134102 of 203Receive DMA Memory Organization Figure 8.1.1BFree Data Buffer SpaceReceive Free Queue Descriptors:Contains 32-Bit Addresses for Free

DS3134103 of 2038.1.2 PACKET DESCRIPTORSIn main memory resides a contiguous section up to 65,536 quad dwords that make up the Receive PacketDescripto

DS3134104 of 203Receive Packet Descriptors Figure 8.1.2Bdword 0Data Buffer Address (32)dword 1BUFS (3) Byte Count (13) Next Descriptor Pointer (16)d

DS3134105 of 2038.1.3 FREE QUEUEThe Host will write to the Receive Free Queue, the 32-bit addresses of the available (i.e. free) data buffersand thei

DS3134106 of 203Empty CaseThe Receive Free Queue is considered empty when the read and write pointers are identical.Receive Free Queue Empty Stateemp

DS3134107 of 203Receive Free Queue Internal Address Storage Table 8.1.3BRegister Name Acronym AddressReceive Free Queue Base Address 0 (lower word)

DS3134108 of 203Receive Free Queue Structure Figure 8.1.3BOnce the Receive DMA is activated (by setting the RDE control bit in the Master Configurat

DS3134109 of 203Status / InterruptsOn each read of the Free Queue by the DMA, the DMA will set either the Status Bit for Receive DMALarge Buffer Read

DS313411 of 203In the receive path, the following process occurs. The HDLC Engines collect the incoming data into32-bit dwords and then signal the F

DS3134110 of 203Register Name: RDMAQRegister Description: Receive DMA Queues ControlRegister Address: 0780h76543210n/a n/a RDQF RDQFE RFQSF RFQLF n/a

DS3134111 of 203dword 0; Bits 0 to 15 / Descriptor Pointer. This 16-bit value is the offset from the Receive DescriptorBase Address of a Receive Pac

DS3134112 of 203The Receive Done Queue is circular queue. To keep track of the addresses of the circular queue in theReceive Done Queue, there are a

DS3134113 of 203Receive Done Queue Internal Address Storage Table 8.1.4ARegister Name Acronym AddressReceive Done Queue Base Address 0 (lower word)

DS3134114 of 203Status Bits / InterruptsOn writes to the Done Queue by the DMA, the DMA will set the Status Bit for Receive DMA DoneQueue Write (RDQW

DS3134115 of 203Done Queue FIFO Flush TimerTo make sure that the Done Queue FIFO does get flushed to the Done Queue on a regular basis, theReceive Do

DS3134116 of 203Bit 4 / Receive Done Queue FIFO Enable (RDQFE). To enable the DMA to burst write descriptors tothe Done Queue; this bit must be set

DS3134117 of 203RECEIVE DMA CONFIGURATION RAM Figure 8.1.5A - FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -dword 0; Bits 0 to 31 / Current Da

DS3134118 of 203- HOST MUST CONFIGURE -dword 2; Bits 1 & 2 / Buffer Size Select. These bits are controlled by the host to select the manner inwh

DS3134119 of 203- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -dword 2; Bits 29 to 31 / Threshold Count. These 3 bits keep track of the numb

DS313412 of 203When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLCpacket data even if it that mea

DS3134120 of 203Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read onlybit will be set to a one.

DS3134121 of 203Transmit DMA Main Operational Areas Table 8.2.1AName Section DescriptionPacketDescriptors8.2.2 A dedicated area of memory that descr

DS3134122 of 203DMA Linking of Packets (Horizontal Link Listing)The transmit DMA also has the ability to link packets together. Internally, the tran

DS3134123 of 203Transmit DMA Operation Figure 8.2.1A00h08hDone Queue Descriptors(circular queue)dmatbd04hFree Desc. Ptr.CH#5StatusFree Desc. Ptr.CH#

DS3134124 of 203Transmit DMA Memory Organization Figure 8.2.1BFree Data Buffer SpaceTransmit Pending Queue Descriptors:Contains Index Pointers to Pa

DS3134125 of 203Transmit DMA Packet Handling Figure 8.2.1CBuffer 1Packet 11st Descriptor(EOF=0/CV=0)Buffer 2Packet 12nd Descriptor(EOF=0/CV=0)Buffer

DS3134126 of 203Transmit DMA Priority Packet Handling Figure 8.2.1DBuffer 1Packet 11st Descriptor(EOF=0/CV=0)Buffer 2Packet 12nd Descriptor(EOF=0/CV

DS3134127 of 203DMA UPDATES TO THE DONE QUEUEThe Host has two options as to when the transmit DMA should write descriptors that have completedtransmi

DS3134128 of 203forcing the CHEN bit to a one. The DMA will not re-enable the channel until it has finished writing all ofthe previously queued desc

DS3134129 of 2038.2.2 Packet DescriptorsIn main memory resides a contiguous section up to 65,536 quad dwords that make up the Transmit PacketDescript

DS313413 of 203DS3134 RESTRICTIONS FOR REV B1/B2 SILICON Table 1DPort maximum of 16 channelized and unchannelized physical portsUnchannelized ports

DS3134130 of 203Transmit Packet Descriptors Figure 8.2.2Bdword 0Data Buffer Address (32)dword 1EOF CV unused Byte Count (13) Next Descriptor Pointer

DS3134131 of 2038.2.3 PENDING QUEUEThe Host will write to the Transmit Pending Queue, the location of the readied descriptor, channelnumber and contr

DS3134132 of 203The Transmit DMA will read from the Transmit Pending Queue Descriptor circular queue which databuffers and their associated descripto

DS3134133 of 203Transmit Pending Queue Internal Address Storage Table 8.2.3ARegister Name Acronym AddressTransmit Pending Queue Base Address 0 (lowe

DS3134134 of 203Pending Queue Burst ReadingThe DMA has the ability to read the Pending Queue in bursts. This allows for a more efficient use of theP

DS3134135 of 203Bit 2 / Transmit Done Queue FIFO Enable (TDQFE). See Section 8.2.4 for details.Bit 3 / Transmit Done Queue FIFO Flush (TDQF). See S

DS3134136 of 203010 = middle buffer transmission complete of a multi-buffer packet (DQS = 1)011 = last buffer transmission complete of a multi-buffer

DS3134137 of 203Transmit Done Queue Internal Address Storage Table 8.2.4ARegister Name Acronym AddressTransmit Done Queue Base Address 0 (lower word

DS3134138 of 203The DMA also checks the Transmit Done Queue Host Read Pointer to make sure that an overflow doesnot occur. If this does occur, then

DS3134139 of 203Register Name: TDQFFTRegister Description: Transmit Done Queue FIFO Flush TimerRegister Address: 0844h76543210TC7 TC6 TC5 TC4 TC3 TC2

DS313414 of 203INITIALIZATIONOn a system reset (which can be invoked by either hardware action via the PRST* signal or softwareaction via the RST con

DS3134140 of 203Bits 8 to 10 / Transmit Done Queue Status Bit Threshold Setting (TDQT0 to TDQT2). These 3 bitsdetermine when the DMA will set the Tr

DS3134141 of 203 - FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -dword 0; Bits 0 to 31 / Current Data Buffer Address. The current 32-bit addre

DS3134142 of 203- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -dword 1; Bits 18 to 19 / Pending State (PENDST). This field is used by the tra

DS3134143 of 203- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -dword 3; Bits 16 to 31 / Last Pending Descriptor Pointer. This 16-bit value is

DS3134144 of 203Bits 8 to 11 / Transmit DMA Configuration RAM Word Select Bits 0 to 3 (TDCW0 to TDCW3).0000 = lower word of dword 00001 = upper word

DS3134145 of 203SECTION 9: PCI BUS9.1 PCI GENERAL DESCRIPTION OF OPERATIONThe PCI Block interfaces the DMA Block to an external high-speed bus. The

DS3134146 of 203PCI Read CycleA read cycle on the PCI bus is shown in Figure 9.1B. During clock cycle #1, the initiator asserts thePFRAME* signal an

DS3134147 of 203PCI Write CycleA write cycle on the PCI bus is shown in Figure 9.1C. During clock cycle #1, the initiator asserts thePFRAME* signal

DS3134148 of 203PCI Bus ArbitrationThe PCI bus can be arbitrated as shown in Figure 9.1D. The initiator will request bus access by assertingPREQ*.

DS3134149 of 203PCI Target RetryTargets can terminate the requested bus transaction before any data is transferred because the target isbusy and temp

DS313415 of 203INDIRECT REGISTERS Table 1ERegister Name (Acronym) Number of Indirect RegistersChannelized Port registers (CP0RD to CP15RD) 6144 (16

DS3134150 of 203PCI Target Disconnect Figure 9.1GPCI Target AbortTargets can also abort the current transaction which means that it does not wish fo

DS3134151 of 203PCI Fast Back-to-Back Figure 9.1J9.2 PCI CONFIGURATION REGISTER DESCRIPTIONRegister Name: PVID0Register Description: PCI Vendor ID /

DS3134152 of 203Register Name: PCMD0Register Description: PCI Command / Status Register 0Register Address: 0x004lsbSTEPC PARC VGA MWEN SCC MASC MSC I

DS3134153 of 203Bit 5 / VGA Control (VGA). This read only bit is forced to zero by the device to indicate that it is not aVGA compatible device.Bit 6

DS3134154 of 203Bit 25 & 26 / Device Timing Select Bits 0 & 1 (DTS0 & DTS1). These two read only bits are forced to01b by the device to

DS3134155 of 203Bits 24 to 31 / Class Code Base Class. These read only bits identify the base class value for the deviceand are fixed at 02h, which

DS3134156 of 203Read only bits in the PDCM register are indicated above by being underlined. All other bits are read-write.Bit 0 / Memory Space Indi

DS3134157 of 203Register Name: PVID1Register Description: PCI Vendor ID / Device ID Register 1Register Address: 0x100lsbVendor ID (Read Only / set to

DS3134158 of 203COMMAND BITSBit 0 / I/O Space Control (IOC). This read only bit is forced to zero by the device to indicate that itdoes not respond

DS3134159 of 203STATUS BITSThe upper word in the PCMD1 register is the Status portion, which report events as they occur. Asmentioned earlier, reads

DS313416 of 203SECTION 2: SIGNAL DESCRIPTION2.1 OVERVIEW / SIGNAL LEAD LISTThis section describes the input and output signals on the DS3134. Signa

DS3134160 of 203Register Name: PRCC1Register Description: PCI Revision ID / Class Code Register 1Register Address: 0x108hlsbRevision ID (Read Only /

DS3134161 of 203Register Name: PLBMRegister Description: PCI Local Bus Memory Base Address RegisterRegister Address: 0x110hlsbBase Address (Read Only

DS3134162 of 203Register Name: PINTL1Register Description: PCI Interrupt Line & Pin / Minimum Grant / Maximum Latency Register 1Register Address:

DS3134163 of 203SECTION 10: LOCAL BUS10.1 LOCAL BUS GENERAL DESCRIPTIONThe Local Bus can operate in two modes, as a PCI Bridge (master mode) and as a

DS3134164 of 203Bridge Mode Figure 10.1ABridge Mode with Arbitration Enabled Figure 10.1BT1 / E1Framer orTransceiverLocal BusDS3134 ChateauHostProc

DS3134165 of 203Configuration Mode Figure 10.1CPCI Bridge ModeIn the PCI Bridge Mode, data from the PCI bus can be transferred to the Local Bus. In

DS3134166 of 203Local Bus 8-Bit Width Address / LBHE* Setting Table 10.1BPCBE*[3:0]A1 A0 LBHE*1110 0 0 11101 0 1 11011 1 0 10111 1 1 1Note:1. All o

DS3134167 of 203Bridge Mode Bus ArbitrationIn the Bridge Mode, the Local Bus has the ability to arbitrate for bus access. In order for the feature t

DS3134168 of 203Local Bus Access Flowchart Figure 10.1DPCI Host Initiates aLocal Bus AccessIs Arbitration Enabledfor the Local Bus?Is the Local BusG

DS3134169 of 20310.2 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTIONRegister Name: LBBMCRegister Description: Local Bus Bridge Mode Control Regist

DS313417 of 203Lead Symbol Type Signal DescriptionK19 LCS* I Local Bus Chip Select.V20 LD0 I/O Local Bus Data Bit 0. LSB.U20 LD1 I/O Local Bus Data

DS3134170 of 2031011 = bus transaction is defined as 11 LCLK periods1100 = illegal state1101 = illegal state1110 = illegal state1111 = illegal stateB

DS3134171 of 20310.3 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODEOPERATIONFigure 10.3A8-Bit Read CycleIntel Mode (LIM = 0)Arbitration Enabled

DS3134172 of 203Figure 10.3B16-Bit Write CycleIntel Mode (LIM = 0)Arbitration Enabled (LARBE = 1)Bus Transaction Time = 4 LCLK (LRDY = 0100)An attemp

DS3134173 of 203Figure 10.3C8-Bit Read CycleIntel Mode (LIM = 0)Arbitration Disabled (LARBE = 0)Bus Transaction Time = Timed from LRDY* (LRDY = 0000)

DS3134174 of 203Figure 10.3D16-Bit Write (only upper 8-bits active) CycleIntel Mode (LIM = 0)Arbitration Disabled (LARBE = 0)Bus Transaction Time = T

DS3134175 of 203Figure 10.3E8-Bit Read CycleMotorola Mode (LIM = 1)Arbitration Enabled (LARBE = 1)Bus Transaction Time = 6 LCLK (LRDY = 0110)An attem

DS3134176 of 203Figure 10.3F8-Bit Write CycleMotorola Mode (LIM = 1)Arbitration Enabled (LARBE = 1)Bus Transaction Time = 6 LCLK (LRDY = 0110)An atte

DS3134177 of 203Figure 10.3G16-Bit Read CycleMotorola Mode (LIM = 1)Arbitration Disabled (LARBE = 0)Bus Transaction Time = Timed from LRDY* (LRDY = 0

DS3134178 of 203Figure 10.3H8-Bit Write CycleMotorola Mode (LIM = 1)Arbitration Disabled (LARBE = 0)Bus Transaction Time = Timed from LRDY* (LRDY = 0

DS3134179 of 203SECTION 11: JTAG11.1 JTAG DESCRIPTIONThe DS3134 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, andEXTEST. Op

DS313418 of 203Lead Symbol Type Signal DescriptionV17 PAD0 I/O PCI Multiplexed Address & Data Bit 0.U16 PAD1 I/O PCI Multiplexed Address & Da

DS3134180 of 203TAP Controller State Machine Figure 11.2ATest-Logic-ResetUpon power-up of the DS3134, the TAP controller will be in the Test-Logic-R

DS3134181 of 203Capture-DRData may be parallel loaded into the Test Data registers selected by the current instruction. If theinstruction does not c

DS3134182 of 203Shift-IRIn this state, the shift register in the Instruction register is connected between JTDI and JTDO and shiftsdata one stage for

DS3134183 of 203SAMPLE/PRELOADA mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. Thedigital I/Os of

DS3134184 of 203Boundary Scan Control Bits Table 11.4ABit Symbol Lead I/O Control Bit Description213 LD.iocntl - - 0=LD0 to LD15 are inputs;1=LD0 to

DS3134185 of 203Bit Symbol Lead I/O Control Bit Description170 LA10 E18 I/O169 LA11 D19 I/O168 LA12 C20 I/O167 LA13 E17 I/O166 LA14 D18 I/O165 LA15 C

DS3134186 of 203Bit Symbol Lead I/O Control Bit Description125 TD13 C7 O124 RC14 B6 I123 RS14 A5 I122 RD14 D7 I121 TC14 C6 I120 TS14 B5 I119 TD14 A4

DS3134187 of 203Bit Symbol Lead I/O Control Bit Description80 RD5 R1 I79 TC5 P3 I78 TS5 R2 I77 TD5 T1 O76 RC6 P4 I75 RS6 R3 I74 RD6 T2 I73 TC6 U1 I72

DS3134188 of 203Bit Symbol Lead I/O Control Bit Description36 PIRDY.iocntl - - 0 = PIRDY* is an input; 1 = PIRDY* is an output35 PIRDY* V10 I/O34 PTR

DS3134189 of 203SECTION 12: AC CHARACTERISTICSABSOLUTE MAXIMUM RATINGS*Voltage on Any Lead with Respect to VSS (except VDD) -0.3V to 5.5VSupply Volta

DS313419 of 203Lead Symbol Type Signal DescriptionV11 PPERR* I/O PCI Parity Error.V4 PREQ* O PCI Bus Request.W3 PRST* I PCI Reset.Y12 PSERR* O PCI Sy

DS3134190 of 203AC CHARACTERISTICS - LAYER ONE PORTS(0°C TO +70°C; VDD = 3.0V TO 3.6V)Parameter Symbol Min Typ Max Units NotesRC / TC Clock Period t1

DS3134191 of 203LAYER ONE PORT AC TIMING DIAGRAM Figure 12ANote:TC and RC are independent from each other. In the above timing diagram, all the sign

DS3134192 of 203LOCAL BUS BRIDGE MODE (LMS = 0) AC TIMING DIAGRAM Figure 12BData ValidLCLKLINT* / LRDY*LHLDA(LBG*) LD[15:0]LA[19:0] / LWR*(LR/W*) /L

DS3134193 of 203AC CHARACTERISTICS - LOCAL BUS IN CONFIGURATION MODE (LMS = 1)(0°C TO +70°C; VDD = 3.0V TO 3.6V)Parameter Symbol Min Typ Max Units No

DS3134194 of 203LOCAL BUS CONFIGURATION MODE (LMS = 1) AC TIMING DIAGRAMFigure 12CIntel Read CycleLOCAL BUS CONFIGURATION MODE (LMS = 1) AC TIMING DI

DS3134195 of 203Motorola Read CycleMotorola Write CycleAddress ValidData ValidLA[15:0]LD[15:0]LR/W*LCS*LDS*t1t2 t3 t4t5t9Address ValidLA[15:0]LD[15:0

DS3134196 of 203AC CHARACTERISTICS - PCI BUS INTERFACE(0°C TO +70°C; VDD = 3.0V TO 3.6V)Parameter Symbol Min Typ Max Units NotesPCLK Period t1 30 40

DS3134197 of 203AC CHARACTERISTICS - JTAG TEST PORT INTERFACE(0°C TO +70°C; VDD = 3.0V TO 3.6V)Parameter Symbol Min Typ Max Units NotesJTCLK Clock Pe

DS3134198 of 203SECTION 13: MECHANICAL DIMENSIONS

DS3134199 of 203SECTION 14: APPLICATIONSSection 14 describes some possible applications for the DS3134. The number of potential configurationsis num

DS31342 of 203There are 16 HDLC Engines (one for each port) that are capable of operating at speeds up to 8.192 Mbpsin channelized mode and up to 10

DS313420 of 203Lead Symbol Type Signal DescriptionM2 RS4 I Receive Serial Sync for Port 4.P2 RS5 I Receive Serial Sync for Port 5.R3 RS6 I Receive Se

DS3134200 of 203QUAD T1/E1 CONNECTION Figure 14C16 Port T1 or E1 with 256 HDLC Channel SupportFigure 14D shows an application where 16 T1 ports are

DS3134201 of 203Dual T3 with 256 HDLC Channel SupportFigure 14E shows an application where two T3 lines are interfaced to a single DS3134. In thisap

DS3134202 of 203Single T3 with 512 HDLC Channel SupportFigure 14F shows an application where a T3 line is interfaced to two DS3134. In this applicat

DS3134203 of 203Single T3 with 672 HDLC Channel SupportFigure 14G shows an application where a T3 line is interfaced to three DS3134. In this applic

DS313421 of 203Lead Symbol Type Signal DescriptionE4 TS0 I Transmit Serial Sync for Port 0.F3 TS1 I Transmit Serial Sync for Port 1.G1 TS2 I Transmit

DS313422 of 203Lead Symbol Type Signal DescriptionU8 VSS - Ground Reference.U12 VSS - Ground Reference.U13 VSS - Ground Reference.U17 VSS - Ground Re

DS313423 of 203RS SAMPLED EDGE Table 2.2ANormal RC Clock Mode Inverted RC Clock Mode0 RC Clock Early Mode falling edge rising edge1/2 RC Clock Early

DS313424 of 2032.3 LOCAL BUS SIGNAL DESCRIPTIONSignal Name: LMSSignal Description: Local Bus Mode SelectSignal Type: InputThis signal should be tied

DS313425 of 203Signal Name: LA0 to LA19Signal Description: Local Bus Non-Multiplexed Address BusSignal Type: Input / Output (tri-state capable)In the

DS313426 of 203Signal Name: LRDY*Signal Description: Local Bus PCI Bridge Ready [PCI Bridge Mode Only]Signal Type: InputThis active low signal is sam

DS313427 of 203Signal Name: LCLKSignal Description: Local Bus Clock [PCI Bridge Mode Only]Signal Type: Output (tri-state capable)This signal outputs

DS313428 of 203Signal Name: JTMSSignal Description: JTAG IEEE 1149.1 Test Mode SelectSignal Type: Input (with internal 10k pull up)This signal is sam

DS313429 of 203Signal Description: PCI Bus ParitySignal Type: Input / Output (tri-state capable)This signal provides information on even parity acros

DS31343 of 203REVISION HISTORYVersion 1 (1/30/98)Original release.Version 2 (4/4/98)1. Assigned signals to leads (Section 2.1).2. Added more info

DS313430 of 203Signal Name: PSTOP*Signal Description: PCI StopSignal Type: Input / Output (tri-state capable)This active low signal is created by the

DS313431 of 203Signal Name: PSERR*Signal Description: PCI System ErrorSignal Type: Output (open drain)This active low signal reports any parity error

DS313432 of 2032.6 SUPPLY & TEST SIGNAL DESCRIPTIONSignal Name: TESTSignal Description: Factory Test InputSignal Type: Input (with internal 10k

DS313433 of 203SECTION 3: MEMORY MAP3.0 INTRODUCTIONAll addresses within the memory map on dword boundaries even though all of the internal deviceco

DS313434 of 2033.2 RECEIVE PORT REGISTERS (1XX)Offset/AddressAcronym Register Name Section0100 RP0CR Receive Port 0 Control Register. 5.20104 RP1CR

DS313435 of 2033.4 CHANNELIZED PORT REGISTERS (3XX)Offset/AddressAcronym Register Name Section0300 CP0RDIS Channelized Port 0 Register Data Indirect

DS313436 of 2033.6 BERT REGISTERS (5XX)Offset/AddressAcronym Register Name Section0500 BERTC0 BERT Control 0. 5.60504 BERTC1 BERT Control 1. 5.60508

DS313437 of 2033.8 TRANSMIT DMA REGISTERS (8XX)Offset/AddressAcronym Register Name Section0800 TPQBA0 Transmit Pending Queue Base Address 0 (lower w

DS313438 of 2033.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX)Offset/AddressAcronym Register Name Section0x100/0B00 PVID1 PCI Vendor ID

DS313439 of 203SECTION 4: GENERAL DEVICE CONFIGURATION & STATUS/INTERRUPT4.1 MASTER RESET & ID REGISTER DESCRIPTIONThe Master Reset & I

DS31344 of 203Version 6 (05/01/00) Rev B1/B2 silicon release1. Typo correction on the following pages: 7, 53, 61, 80, 107, 114 and 1152. Add (notes

DS313440 of 203Bit 0 / Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to zero,the receive DMA will not pass a

DS313441 of 203Bits 7 to 11 / BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These 5 bits select which port has thededicated resources of the BERT.000

DS313442 of 203SM RegisterThe Status Master (SM) register reports events that occur at the Port Interface, at the BERT receiver, atthe PCI Bus and at

DS313443 of 203STATUS REGISTER BLOCK DIAGRAM FOR SM & SV54 Figure 4.3.1APort I/F # 0#1#2#3#13#14#15#1#2#3#13#14#15OR ORReceiveORSRCOFASTCOFASBER

DS313444 of 2034.3.2 STATUS & INTERRUPT REGISTER DESCRIPTIONRegister Name: SMRegister Description: Status Master RegisterRegister Address: 0020h

DS313445 of 203Bit 4 / Status Bit for PCI System Error (PPERR). This status bit is a software version of the PCI Bushardware pin PPERR. It will be

DS313446 of 203Bit 3 / Status Bit for PCI System Error (PSERR).0 = interrupt masked1 = interrupt unmaskedBit 4 / Status Bit for PCI System Error (PPE

DS313447 of 203Register Name: ISV54Register Description: Interrupt Mask Register for SV54Register Address: 0034h76543210SLBP7 SLBP6 SLBP5 SLBP4 SLBP3

DS313448 of 203will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if theLocal Bus is in the Configuration

DS313449 of 203Bit 11 / Status Bit for Receive DMA Done Queue Write Error (RDQWE). This status bit will be setto a one each time the Receive DMA tri

DS31345 of 203TABLE OF CONTENTSSection 1: Introduction……………………………………………………………………………………..7Section 2: Signal Description……………………………………………………………………………

DS313450 of 203Register Name: ISDMARegister Description: Interrupt Mask Register for SDMARegister Address: 002Ch76543210RLBRE RLBR ROVFL RLENC RABRT

DS313451 of 203Bit 11 / Status Bit for Receive DMA Done Queue Write Error (RDQWE).0 = interrupt masked1 = interrupt unmaskedBit 12 / Status Bit for T

DS313452 of 203SECTION 5: LAYER ONE5.1 GENERAL DESCRIPTIONThe Layer One Block is shown in Figure 5.1A. Each of the 16 Layer One ports on the DS313

DS313453 of 203Each port contains a Layer One State Machine, which connects directly to the Slow HDLC Engine. TheLayer One State Machine prepares th

DS313454 of 203LAYER ONE BLOCK DIAGRAM Figure 5.1ARSRCRDSLOWHDLC(OneperPort)FASTHDLCLayer OneState MachineReceiveTransmitChannel-izedLocalLoop-Back(

DS313455 of 203PORT TIMING (FOR CHANNELIZED AND UNCHANNELIZED APPLICATIONS)Figure 5.1BRC[n] / TC[n]Normal ModeRD[n]TD[n]RS[n] / TS[n]0 Clock Early &a

DS313456 of 2035.2 PORT REGISTER DESCRIPTIONSReceive Side Control Bits (one each for all 16 ports)Register Name: RP[n]CR where n = 0 to 15 for each

DS313457 of 203Bit 6 / Sync Select Bit 0 (RSS0).Bit 7 / Sync Select Bit 1 (RSS1).These 2 bits select the mode in which each port is to be operated. E

DS313458 of 203Bit 15 / COFA Status Bit (RCOFA). This latched read only status bit will be set if a Change Of FrameAlignment is detected. The COFA

DS313459 of 203Bit 6 / Sync Select Bit 0 (TSS0).Bit 7 / Sync Select Bit 1 (TSS1).These 2 bits select the mode in which each port is to be operated.

DS31346 of 203Section 7: FIFO………………………………………………………………………………………… 857.1 General Description & Example…………………………………………………………. 857.2 FIFO Register

DS313460 of 2035.3 LAYER ONE CONFIGURATION REGISTER DESCRIPTIONThere are three configuration registers for each DS0 channel on each port. These thr

DS313461 of 203Port Mode DS0 ChannelsAvailableUnchannelized Mode (RUEN/TUEN = 1)0Channelized T1 Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 0 & RSS1/TS

DS313462 of 203Register Name: CP[n]RD where n = 0 to 15 for each PortRegister Description: Channelized Port [n] Register DataRegister Address: See th

DS313463 of 203Register Name: C[n]DAT[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0Register Description: Channelized Layer 1 DS0

DS313464 of 203Bit 8 / Receive 56 kbps (R56). If the Port is running a channelized application, this bit determineswhether the LSB of each DS0 shoul

DS313465 of 203Bits 0 to 7 / Transmit Channel Number (TCH#). The CPU will load the number of the HDLC channelassociated with this particular DS0 cha

DS313466 of 203Bit 15 / Transmit DS0 Channel Enable (TCHEN). This bit must be set for each active DS0 channel ina channelized application. In a cha

DS313467 of 203Receive V.54 Search Routine Table 5.4AStep #1: Set Up the Channel SearchThe Host will determine in which DS0 channels the V.54 search

DS313468 of 203Receive V.54 Host Algorithm Figure 5.4ASet Up theDS0 ChannelSearchToggle VRSTWait forSLBP = 1VTO = 1?Place DS0Channels intoLoopbackYe

DS313469 of 203Receive V.54 State Machine Figure 5.4BVRST = 1VLB = 0VTO = 0SLBP = 0Search forLoop UpPattern for32 VCLKsReset 4 second timer;wait fo

DS31347 of 203SECTION 1: INTRODUCTIONThe DS3134 Chateau device is a 256 channels HDLC controller. The primary features of the device arelisted in Tab

DS313470 of 2035.5 BERTThe BERT Block is capable of generating and detecting the following patterns:- The pseudorandom patterns 2E7, 2E11, 2E15, and

DS313471 of 2035.6 BERT REGISTER DESCRIPTIONBERT Register Set Figure 5.6ABERTC0: BERT Control 0 lsbn/a TINV RINV PS2 PS1 PS0 LC RESYNCmsbIESYNC IEB

DS313472 of 203Register Name: BERTC0Register Description: BERT Control Register 0Register Address: 0500h7654321 0n/a TINV RINV PS2 PS1 PS0 LC RESYNC1

DS313473 of 203Bit 11 / Repetitive Pattern Length Bit 3 (RPL3).RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repeti

DS313474 of 203Bit 4 / Single Bit Error Insert (SBE). A low to high transition will create a single bit error. Must becleared and set again for a s

DS313475 of 203BERTRP1: BERT Repetitive Pattern Set 1 (upper word)23 22 21 20 19 18 17 16BERT Repetitive Pattern Set31 30 29 28 27 26 25 24BERT Repet

DS313476 of 203Bits 0 to 31 / BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter willincrement for each data bit (i.e. clock) receiv

DS313477 of 203Register Name: BERTEC1Register Description: BERT 24-Bit Error Counter (upper)Register Address: 051Ch76543210BERT 24-Bit Error Counter1

DS313478 of 203SECTION 6: HDLC6.1 GENERAL DESCRIPTIONThe DS3134 contains two different types of HDLC controllers. Each port has a Slow HDLC Engine

DS313479 of 203If any of the 256 receive HDLC channels detects an abort sequence, a FCS checksum error, or if thepacket length was incorrect, then th

DS31348 of 203DS3134 FEATURE LIST Table 1ALayer Can Support Up to 64 T1 or E1 Data Streams or Two T3 Data StreamsOne 16 Independent Physical Ports

DS313480 of 203Transmit HDLC Functions Table 6.1CZero Stuffing- Only used in between opening and closing flags.- Will be disabled in between a closi

DS313481 of 203Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internalReceive HDLC Definition RAM, this bit

DS313482 of 203Bit 2 & Bit 3 / Receive CRC Selection (RCRC0/RCRC1). These 2 bits are ignored if the HDLCchannel is set into Transparent mode (RT

DS313483 of 203Register Name: RHPLRegister Description: Receive HDLC Maximum Packet LengthRegister Address: 0410h76543210RHPL7 RHPL6 RHPL5 RHPL4 RHPL

DS313484 of 203Register Name: THCDRegister Description: Transmit HDLC Channel DefinitionRegister Address: 0484h7654321 0TABTE TCFCS TBF TID TCRC1 TCR

DS313485 of 203Bit 6 / Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC engine will allow theFrame Checksum Sequence (FCS) to be tra

DS313486 of 203SECTION 7: FIFO7.1 GENERAL DESCRIPTION & EXAMPLEChateau contains one 16k byte FIFO for the receive path and another 16k byte FIF

DS313487 of 203Starting Block Pointer. The Block Pointer RAM tells the device how to link the eight Blocks together toform a circular chain.The Host

DS313488 of 203Receive High Water MarkThe High Water Mark indicates to the device how many Blocks should be written into the receive FIFOby the HDLC

DS313489 of 203Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).00000000 (00h) = HDLC Channel Number 111111111 (FFh) = HDLC Channel Number 256Bit 14 /

DS31349 of 203Local Can Operate as a Bridge from the PCI Bus or a Configuration BusBus In Bridge Mode; can arbitrate for the Bus8 or 16 Bits WideIn B

DS313490 of 203Register Name: RFBPISRegister Description: Receive FIFO Block Pointer Indirect SelectRegister Address: 0910h76543210BLKID7 BLKID6 BLKI

DS313491 of 203Register Description: Receive FIFO High Water Mark Indirect SelectRegister Address: 0920h76543210HCID7 HCID6 HCID5 HCID4 HCID3 HCID2 H

DS313492 of 2030000000010 (002h) = High Water Mark is 2 Blocks0111111111 (1FFh) = High Water Mark is 511 Blocks1111111111 (3FFh) = High Water Mark is

DS313493 of 203Bits 0 to 9 / Starting Block Pointer (TSBP0 to TSBP9). These 10 bits determine which of the 1024blocks within the transmit FIFO, the

DS313494 of 203Register Name: TFBPRegister Description: Transmit FIFO Block PointerRegister Address: 0994h76543210TBP7 TBP6 TBP5 TBP4 TBP3 TBP2 TBP1

DS313495 of 203Register Name: TFLWMRegister Description: Transmit FIFO Low Water MarkRegister Address: 09A4h76543210TLWM7 TLWM6 TLWM5 TLWM4 TLWM3 TLW

DS313496 of 203SECTION 8: DMA8.0 INTRODUCTIONThe DMA block (see Figure 1.1A) handles the transfer of packet data from the FIFO block to the PCIbloc

DS313497 of 203DMA Registers that must be configured by the Host on Power-Up Table 8.0AAddress Acronym Register Section0700 RFQBA0 Receive Free Queu

DS313498 of 2038.1 RECEIVE SIDE8.1.1 OVERVIEWThe receive DMA uses a scatter gather technique to write packet data into main memory. The Host willke

DS313499 of 203Bits 0 to 12 / Small Buffer Select Bit (SBS0 to SBS12).0000000000000 (0000h) = Buffer Size is 0 Bytes1111111111111 (1FFFh) = Buffer Si