Rainbow-electronics DS3170 Bedienungsanleitung Seite 218
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DS3170 DS3/E3 Single-Chip Transceiver
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17 AC TIMING CHARACTERISTICS
There are several common AC characteristic definitions. These generic definitions are shown in Figure 17-1,
Figure 17-2
, Figure 17-3, and Figure 17-4. Definitions that are specific to a given interface are shown in that
interface’s subsection.
Figure 17-1. Clock Period and Duty Cycle Definitions
Clock
t1
t2t2
Figure 17-2. Rise Time, Fall Time, and Jitter Definitions
Clock
t1
t4
t3 t3
t4/2
Figure 17-3. Hold, Setup, and Delay Definitions (Rising Clock Edge)
Clock
Signal
t5 t6
Signal
t7
- DS3/E3 Single-Chip Transceive 1
- DETAILED DESCRIPTION 2
- 1 BLOCK DIAGRAMS 2
- Figure 1-2. Block Diagram 3
- TABLE OF CONTENTS 4
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- 18 REVISION HISTORY 233 7
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- 2 APPLICATIONS 12
- 3 FEATURE DETAILS 13
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- 4 STANDARDS COMPLIANCE 16
- 5 ACRONYMS AND GLOSSARY 17
- 6 MAJOR OPERATIONAL MODES 18
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- 6.5 DS3/E3 Framed UNI Mode 23
- 7 PIN DESCRIPTIONS 25
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- 7.3 Pin Functional Timing 37
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- Figure 7-30. 8-Bit Mode Read 47
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- 9 FUNCTIONAL DESCRIPTION 53
- 9.1.8 Interrupt Structure 54
- 9.2 Clocks 55
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- Table 9-1. LIU Enable Table 57
- PORT.CR3 58
- LOOPBACK 58
- DIAGNOSTIC 59
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- 9.3 Reset and Power-Down 63
- Figure 9-5. Reset Sources 64
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- 9.4 Global Resources 66
- Figure 9-6. 8KREF Logic 67
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- 9.5 Port Resources 71
- Figure 9-9. Loopback Modes 72
- Figure 9-10. ALB Mux 72
- 9.5.3 AIS Logic 73
- LINE/TRIBUTARY 74
- TRUNK SIDE 74
- 9.5.4 Loop Timing Mode 75
- 9.5.6 Trail Trace 75
- 9.5.7 BERT 75
- 9.5.8 System Port Pins 76
- 9.5.9 Framing Modes 77
- 9.5.10 Line Interface Modes 77
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- 9.6.1 General Description 79
- 9.6.2 Features 79
- 9.6.3 Transmit Formatter 80
- 9.6.4 Receive Framer 80
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- 1524 Bit Payload 89
- 384 bits 89
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- 9.7.1 General Description 96
- 9.7.2 Features 97
- 9.7.3 Transmit FIFO 97
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- 9.8 Trail Trace Controller 99
- 9.8.2 Features 100
- 9.8.3 Functional Description 100
- 9.8.4 Transmit Data Storage 101
- 9.8.9 Receive Data Storage 102
- 9.9.1 General Description 102
- 9.9.2 Features 103
- 9.9.3 Functional Description 103
- 9.10 Line Encoder/Decoder 104
- 9.10.2 Features 105
- 9.10.3 B3ZS/HDB3 Encoder 105
- 9.10.6 B3ZS/HDB3 Decoder 106
- Figure 9-25. B3ZS Signatures 107
- Figure 9-26. HDB3 Signatures 107
- 9.11.1 General Description 108
- 9.11.2 Features 108
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- LoadVerify 110
- MatchVerify 111
- 9.12.1 General Description 112
- 9.12.2 Features 112
- 9.12.3 Detailed Description 112
- 9.12.4 Transmitter 113
- 9.12.5 Receiver 114
- INT pin if enabled 115
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- 10 OVERALL REGISTER MAP 117
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- 11.1 Registers Bit Maps 119
- 11.1.3 T3 Register Bit Map 123
- 11.2 Global Registers 126
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- INT pin will be driven low 130
- INT pin 131
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- 11.3 Port Register 133
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- RST and the GL.CR1.RST bit 135
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- 11.4 BERT 144
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- 11.6 HDLC 156
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- 11.7 FEAC Controller 163
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- 11.8 Trail Trace 168
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- 12 JTAG INFORMATION 202
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- 12.4 JTAG ID Codes 206
- Table 12-2. JTAG ID Codes 206
- 12.6 IO Pins 207
- 13 PIN CONFIGURATIONS 208
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- 14 PACKAGE INFORMATION 213
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- Table 16-3. Output Pin Drive 217
- 17 AC TIMING CHARACTERISTICS 218
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- 17.3.1 SPI Bus Mode 222
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- 17.3.2 Parallel Bus Mode 224
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- 17.5.1 Waveform Templates 227
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- 18 REVISION HISTORY 233
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