
DS1215
032697 11/15
TIMING DIAGRAM: READ CYCLE ROM/RAM = V
CCO
OUTPUT DATA VALID
t
RC
t
CO
t
RR
t
OD
t
RR
t
RC
t
OE
t
AS
t
AS
t
OEE
t
COE
t
ODO
t
AH
t
AH
CEI
OE
WE
Q
TIMING DIAGRAM: WRITE CYCLE ROM/RAM = V
CCO
DATA IN STABLE
t
WC
t
CW
t
WR
t
WR
t
WC
t
OW
t
AS
t
AS
t
AH
t
AH
CEI
OE
WE
D
t
DS
t
DS
t
DH
t
DH
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