
DS1339
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Figure 4. SQUARE-WAVE OUTPUT FREQUENCY
RS2 RS1
SQUARE-WAVE OUTPUT
FREQUENCY
0 0 1Hz
0 1 4.096kHz
1 0 8.192kHz
1 1 32.768kHz
INTCN (Interrupt Control) – This bit controls the relationship between the two alarms and the interrupt
output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the
Alarm 1 or Alarm 2 registers activate the SQW/INT pin (provided that the alarms are enabled).When the
INTCN bit is set to logic 0, a square wave is output on the SQW/ INT pin. This bit is set to logic 0 when
power is first applied.
A1IE (Alarm 1 Interrupt Enable) – When set to logic 1, this bit permits the A1F bit in the status
register to assert SQW/ INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the an interrupt signal. The A1IE bit is disabled (logic 0) when
power is first applied.
A2IE (Alarm 2 Interrupt Enable) – When set to a logic 1, this bit permits the A2F bit in the status
register to assert SQW/ INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is
first applied.
STATUS REGISTER (0Fh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSF 0 0 0 0 0 A2F A1F
OSF (Oscillator Stop Flag) – A logic 1 in this bit indicates that the oscillator either is stopped or was
stopped for some period of time and can be used to judge the validity of the clock and date data. This bit
is edge-triggered and set to logic 1 anytime the oscillator stops. The following are examples of conditions
that can cause the OSF bit to be set:
1) The first time power is applied.
2) The voltage present on both V
CC
and V
BACKUP
are insufficient to support oscillation.
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0. Attempting to
write to logic 1 leaves the value unchanged.
A1F (Alarm 1 Flag) – A logic 1 in the A1F bit indicates that the time matched the Alarm 1 registers. If
the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/ INT pin is also be asserted. A1F
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