Rainbow-electronics DS1672 Bedienungsanleitung PDF herunterladen (Seite 4)

DS1672

4 of 12

AC ELECTRICAL CHARACTERISTICS

> V

CCMIN

, T

= -40°C to +85°C)

PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NOTES

Fast Mode 100 400

SCL Clock

Frequency

SCL

Standard Mode 100

kHz

Fast Mode 1.3

Bus Free Time

Between a STOP and

START Condition

BUF

Standard Mode 4.7

Fast Mode 0.6

Hold Time

(Repeated) START

Condition

HD:STA

Standard Mode 4.0

Fast Mode 1.3

LOW Period of SCL

Clock

LOW

Standard Mode 4.7

Fast Mode 0.6

HIGH Period of SCL

Clock

HIGH

Standard Mode 4.0

Fast Mode 0.6

Setup Time for a

Repeated START

Condition

SU:STA

Standard Mode 4.7

Fast Mode 0 0.9

Data Hold Time t

HD:DAT

Standard Mode 0

7, 8

Fast Mode 100

Data Setup Time t

SU:DAT

Standard Mode 250

ns 9

Fast Mode 20 + 0.1C

300

Rise Time of Both

SDA and SCL

Signals

Standard Mode 1000

ns 10

Fast Mode 20 + 0.1C

300

Fall Time of Both

SDA and SCL

Signals

Standard Mode 300

ns 10

Fast Mode 0.6

Setup Time for STOP

Condition

SU:STO

Standard Mode 4.0

Capacitive Load for

Each Bus Line

400 pF 10

I/O Capacitance C

I/O

10 pF

Note 6: After this period, the first clock pulse is generated.

Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the V

IHMIN

of the SCL signal) in order to

bridge the undefined region of the falling edge of SCL.

Note 8:The maximum t

HD:DAT

has only to be met if the device does not stretch the LOW period (t

LOW

) of the SCL signal.

Note 9: A fast mode device can be used in a standard mode system, but the requirement t

SU:DAT

>= to 250ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW

period of the SCL signal, it must output the next data bit to the SDA line t

max + t

SU:DAT

= 1000 + 250 = 1250ns before the SCL line is

released.

Note 10: C

– Total capacitance of one bus line in pF.

1 2 3 4 5 6 7 8 9 10 11 12

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