DS3903
Triple 128-Position Nonvolatile
Digital Potentiometer
4 ______________________________________________________________________
Note 1: All voltages are referenced to ground.
Note 2: I
STBY
specified for V
CC
equal to 3.0V and 5.0V while control port logic pins are driven to the appropriate
logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or V
CC
for the
corresponding inactive state. WP must be disconnected or connected high.
Note 3: I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
Note 4: A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal.
If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line t
RMAX
+ t
SU:DAT
= 1000ns + 250ns = 1250ns before the SCL line is released.
Note 5: After this period, the first clock pulse is generated.
Note 6: The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the
SCL signal.
Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IN MIN
of
the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
Note 8: C
B
—total capacitance of one bus line in picofarads, timing referenced to 0.9 x V
CC
and 0.1 x V
CC
.
Note 9: EEPROM write begins after a stop condition occurs.
Note 10: Absolute linearity is used to measure expected wiper voltage as determined by wiper position in a
voltage-divider configuration.
Note 11: Relative linearity is used to determine the change of wiper voltage between two adjacent wiper positions
in a voltage-divider configuration.
Typical Operating Characteristics
(V
CC
= 5.0V, 10kΩ plots apply to both pot0 and pot2, T
A
= +25°C unless otherwise noted.)
Kommentare zu diesen Handbüchern