1 of 20 043001 FEATURES • Unique 1-wire interface requires only one port pin for communication • Each device has a unique 64-bit serial co
DS18B20 10 of 20 SKIP ROM [CCh] The master can use this command to address all devices on the bus simultaneously without sending out any ROM code in
DS18B20 11 of 20 is issued the master must enable a strong pullup on the 1-wire bus for at least 10 ms as described in the POWERING THE DS18B20 sect
DS18B20 12 of 20 ROM COMMANDS FLOW CHART Figure 11 CCh SKIP ROM COMMAND MASTER TX RESET
DS18B20 13 of 20 DS18B20 FUNCTION COMMANDS FLOW CHART Figure 12 MASTER TX FUNCTION COMMAND YN 44h CONVERT TEMPERATURE ? PARASITE POWER ? N Y DS18B
DS18B20 14 of 20 1-WIRE SIGNALING The DS18B20 uses a strict 1-wire communication protocol to insure data integrity. Several signal types are defined
DS18B20 15 of 20 The DS18B20 samples the 1-wire bus during a window that lasts from 15 µs to 60 µs after the master initiates the write time slot.
DS18B20 16 of 20 Therefore, the master must release the bus and then sample the bus state within 15 µs from the start of the slot. Figure 15 illustr
DS18B20 17 of 20 DS18B20 OPERATION EXAMPLE 1 In this example there are multiple DS18B20s on the bus and they are using parasite power. The bus mast
DS18B20 18 of 20 ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to ground –0.5V to +6.0V Operating temperature –55°C to +125°C Storage temp
DS18B20 19 of 20 AC ELECTRICAL CHARACTERISTICS: NV MEMORY (-55°C to +100°C; VDD=3.0V to 5.5V) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS NV Wri
DS18B20 2 of 20 DETAILED PIN DESCRIPTIONS Table 1 8-PIN SOIC* TO-92 SYMBOL DESCRIPTION 5 1 GND Ground. 4 2 DQ Data Input/Output pin. Open-drain
DS18B20 20 of 20 TIMING DIAGRAMS Figure 18
DS18B20 3 of 20 OPERATION – MEASURING TEMPERATURE The core functionality of the DS18B20 is its direct-to-digital temperature sensor. The resolution
DS18B20 4 of 20 OPERATION – ALARM SIGNALING After the DS18B20 performs a temperature conversion, the temperature value is compared to the user-defin
DS18B20 5 of 20 The use of parasite power is not recommended for temperatures above 100°C since the DS18B20 may not be able to sustain communication
DS18B20 6 of 20 MEMORY The DS18B20’s memory is organized as shown in Figure 7. The memory consists of an SRAM scratchpad with nonvolatile EEPROM st
DS18B20 7 of 20 CONFIGURATION REGISTER Byte 4 of the scratchpad memory contains the configuration register, which is organized as illustrated in Fig
DS18B20 8 of 20 check is available in Application Note 27 entitled “Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch
DS18B20 9 of 20 TRANSACTION SEQUENCE The transaction sequence for accessing the DS18B20 is as follows: Step 1. Initialization Step 2. ROM Command
Kommentare zu diesen Handbüchern