
7
4866A–GPS–08/05
ATR0601 [Preliminary]
8. Timing
Figure 8-1. Recommended Power-up/down Sequence
Figure 8-2. Recommended Sleep-mode Sequence
Figure 8-3. Recommended XTO Start-up/Shut-down Sequence
Figure 8-4. Sample Clock Start-up Delay
VCC
VDIG
PUxto
PUrf
tmin = 0s
tmin = 0s
tmin = 0s
tmin = 0s tmin=0s tmin = 0s
tmin = 5ms
PUxto
VCC
VDIG
PUrf
tmin = 0s
tmin = 0s
tmin = 4 µs
PUxto
VCC
VDIG
tmin = 1 ms tmin = 4 µs
PUxto
VCC
VDIG
SC
tmax = 500 µs T = 1/23.104 MHz
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