
8
4891CS–GPS–01/06
ATR0622 [Preliminary]
JTAG/ICE
TMS Test Mode Select Input – Internal pull-up resistor
TDI Test Data In Input – Internal pull-up resistor
TDO Test Data Out Output –
TCK Test Clock Input – Internal pull-up resistor
NTRST Test Reset Input Input Low Internal pull-down resistor
DBG_EN Debug Enable Input High Internal pull-down resistor
CLOCK
CLK23 Clock Input Input –
Interface to ATR0601,
Schmitt trigger input
MCLK_OUT Master Clock Output Output – PIO-controlled after reset
RESET NRESET Reset Input I/O Low
Open drain with internal pull-up
resistor
POWER
VDD18 Power – Core voltage 1.8V
VDDIO Power – Variable IO voltage 1.65V to 3.6V
VDD_USB Power –
USB voltage 0 to 2.0V or
3.0V to 3.6V
(1)
GND Power – Ground
LDOBAT
LDOBAT_IN Power – 2.3V to 3.6V
VBAT Power – 1.5V to 3.6V
VBAT18 Out – 1.8V backup voltage
LDO18
LDO_IN LDO In Power – 2.3V to 3.6V
LDO_OUT LDO Out Power – 1.8V core voltage, max. 80 mA
LDO_EN LDO Enable Input –
Table 3-2. ATR0622 Signal Description (Continued)
Module Name Function Type Active Level Comment
Note: 1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND
(internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V.
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