7
4574CS–GPS–05/05
ATR0620 [Preliminary]
138 (1) A7 TMON21 (1) (1) (1) (1) (1)
139 (1) B6 TMON22 (1) (1) (1) (1) (1)
140 (1) Q5 TMON23 (1) (1) (1) (1) (1)
141 (1) Q4 TMON24 (1) (1) (1) (1) (1)
142 (1) N5 TMON25 (1) (1) (1) (1) (1)
143 (1) P3 TMON26 (1) (1) (1) (1) (1)
144 (1) K14 POR_VEXT (1) (1) (1) (1) (1)
Table 1-1. Pin Configuration (Continued)
Serial
Number BGA 100 CPGA 144 Pin Name
Firmware
Label
PIO Bank A PIO Bank B
IOIO
Note: 1. No selection option for PIO.
Table 1-2. Pin Description
Module Name
Function
Type Active Level Comment
EBI
EM_A0 – 23 Address bus Output – All valid after reset
EM_DA0 – 31 Data bus I/O – –
NCS0 – NCS3 Chip select I/O Low –
NWR0 Lower byte 0 write signal I/O Low Used in byte write option
NWR1 Lower byte 0 write signal I/O Low Used in byte write option
NRD Read signal I/O Low Used in byte write option
NWE Write enable I/O Low Used in byte select option
NOE Output enable I/O Low Used in byte select option
NUB Upper byte select (16-bit SRAM) I/O Low Used in byte select option
NLB Lower byte select (16-bit SRAM) Output Low Used in byte write option
NWAIT Wait signal I/O Low –
BOOT_MODE0 Boot mode input I/O – PIO-controlled after reset, pull up
BOOT_MODE1 Boot mode input I/O – PIO-controlled after reset, pull down
USART
TXD0-2 Transmit data output I/O – PIO-controlled after reset
RXD0-2 Receive data input I/O – PIO-controlled after reset
SCK0-2 External serial clock I/O – PIO-controlled after reset
AIC EXTINT0-2 External interrupt request I/O High/Low PIO-controlled after reset
PWM AGCOUT0-1 Automatic gain control Output – PIO-controlled after reset
PMC RF_ON – – – ATR0600
RTC
nSleep Clear sleep output (AF-LDO) Output Low PIO-controlled after reset
nSHDN Clear sleep output (1.8LDO) I/O Low PIO-controlled after reset
XT_IN Oscillator input Input – OSC
XT_OUT Oscillator output Output – OSC
SPI
SCK SPI clock I/O – PIO-controlled after reset
MOSI Master out slave in I/O – PIO-controlled after reset
MISO Master in slave out I/O – PIO-controlled after reset
NPCS0-3 Slave select I/O Low PIO-controlled after reset
WD NWD_OVF Watchdog timer overflow I/O – PIO-controlled after reset
PIO PDSR0-31 Programmable I/O port I/O – Input after reset
(26 Seiten)
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