Rainbow-electronics AT89S53 Bedienungsanleitung

1Features• Compatible with MCS-51™ Products• 12K Bytes of In-System Reprogrammable Downloadable Flash Memory– SPI Serial Interface for Program Downloa

AT89S5310Capture ModeIn the capture mode, two options are selected by bitEXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timeror counter which upon

AT89S5311Figure 2. Timer 2 in Auto Reload Mode (DCEN = 0)Table 9. T2MOD—Timer 2 Mode Control RegisterT2MOD Address = 0C9H Reset Value = XXXX XX00BNo

AT89S5312Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)Figure 4. Timer 2 in Baud Rate Generator ModeOSCSMOD1RCLKTCLKRxCLOCKTxCLOCKT2EX PINT2 PINTR2

AT89S5313Baud Rate GeneratorTimer 2 is selected as the baud rate generator by settingTCLK and/or RCLK in T2CON (Table 2). Note that thebaud rates for

AT89S5314Figure 5. Timer 2 in Clock-Out ModeFigure 6. SPI Block DiagramOSCILLATOR8/16-BIT SHIFT REGISTERREAD DATA BUFFERPIN CONTROL LOGICSPI CONTROL

AT89S5315UARTThe UART in the AT89S53 operates the same way as theUART in the AT89C51, AT89C52 and AT89C55. For fur-ther information, see the October 1

AT89S5316Figure 9. SPI Transfer Format with CPHA = 1*Not defined but normally LSB of previously transmitted characterInterruptsThe AT89S53 has a tota

AT89S5317Timer 2 interrupt is generated by the logical OR of bits TF2and EXF2 in register T2CON. Neither of these flags iscleared by hardware when the

AT89S5318Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked bysoftware. The cont

AT89S5319Programming the FlashAtmel’s AT89S53 Flash Microcontroller offers 12K bytes ofin-system reprogrammable Flash Code memory.The AT89S53 is norma

AT89S532Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sink eig

AT89S5320Reading the Signature Bytes: The signature bytes areread by the same procedure as a normal verification oflocations 030H and 031H, except tha

AT89S5321.Notes: 1. “h” = weakly pulled “High” internally.2. Chip Erase and Serial Programming Fuse require a 10 ms PROG pulse. Chip Erase needs to be

AT89S5322Figure 13. Programming the Flash MemoryFigure 14. Verifying the Flash MemoryFigure 15. Flash Serial DownloadingP1P2.6P3.6P2.0 - P2.5A0 -

AT89S5323Flash Programming and Verification Characteristics – Parallel ModeTA = 0°C to 70°C, VCC = 5.0V ± 10%Symbol Parameter Min Max UnitsVPPProgramm

AT89S5324Flash Programming and Verification Waveforms – Parallel ModeSerial Downloading WaveformsSERIAL CLOCK INPUTSERIAL DATA INPUTSCK/P1.7MOSI/P1.5M

AT89S5325Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:Maximum IOL per port pin: 10 mAMaximum IOL

AT89S5326AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all otheroutput

AT89S5327External Program Memory Read CycleExternal Data Memory Read Cycle

AT89S5328External Data Memory Write CycleExternal Clock Drive WaveformsExternal Clock DriveSymbol Parameter VCC = 4.0V to 6.0VMin Max Units1/tCLCLOsci

AT89S5329.Shift Register Mode Timing WaveformsAC Testing Input/Output Waveforms(1)Notes: 1. AC Inputs during testing are driven at VCC - 0.5V for a lo

AT89S533Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7FLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDPTRINSTRUCTIONREGI

AT89S5330Notes: 1. XTAL1 tied to GND for ICC (power-down)2. Lock bits programmed

AT89S5331Ordering InformationSpeed(MHz)PowerSupplyOrdering Code Package Operation Range24 4.0V to 6.0V AT89S53-24ACAT89S53-24JCAT89S53-24PC44A44J40P6C

AT89S5332Packaging InformationControlling dimension: millimeters1.20(0.047) MAX10.10(0.394)9.90(0.386)SQ12.21(0.478)11.75(0.458)SQ0.75(0.030)0.45(0.01

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

AT89S534Some Port 1 pins provide additional functions. P1.0 andP1.1 can be configured to be the timer/counter 2 externalcount input (P1.0/T2) and the

AT89S535EA/VPPExternal Access Enable. EA must be strapped to GND inorder to enable the device to fetch code from external pro-gram memory locations st

AT89S536Special Function RegistersA map of the on-chip memory area called the Special Func-tion Register (SFR) space is shown in Table 1.Note that not

AT89S537SPI Registers Control and status bits for the Serial Periph-eral Interface are contained in registers SPCR (shown inTable 4) and SPSR (shown i

AT89S538Table 4. SPCR—SPI Control RegisterSPCR Address = D5H Reset Value = 0000 01XXBSPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0Bit76543210Symbol Function

AT89S539Data Memory - RAMThe AT89S53 implements 256 bytes of RAM. The upper128 bytes of RAM occupy a parallel space to the SpecialFunction Registers.