Rainbow-electronics AT90LS2343 Bedienungsanleitung

1Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 118 Powerful Instructions – Most Single Clock

10AT90S/LS2323/23431004D–09/01X-register, Y-register and Z-registerThe registers R26..R31 have some added functions to their general-purpose usage.The

11AT90S/LS2323/23431004D–09/01SRAM Data Memory Figure 9 shows how the AT90S2323/2343 Data Memory is organized.Figure 9. SRAM OrganizationThe 224 data

12AT90S/LS2323/23431004D–09/01Program and Data Addressing ModesThe AT90S2323/2343 AVR RISC microcontroller supports powerful and efficientaddressing m

13AT90S/LS2323/23431004D–09/01I/O Direct Figure 12. I/O Direct AddressingOperand address is contained in six bits of the instruction word. n is the d

14AT90S/LS2323/23431004D–09/01Data Indirect Figure 15. Data Indirect AddressingOperand address is the contents of the X-, Y-, or the Z-register.Data

15AT90S/LS2323/23431004D–09/01Constant Addressing Using the LPM InstructionFigure 18. Code Memory Constant AddressingConstant byte address is specifi

16AT90S/LS2323/23431004D–09/01Memory Access and Instruction Execution TimingThis section describes the general access timing concepts for instruction

17AT90S/LS2323/23431004D–09/01Figure 23. On-chip Data SRAM Access CyclesI/O Memory The I/O space definition of the AT90S2323/2343 is shown in Table 2

18AT90S/LS2323/23431004D–09/01and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers asSRAM, $20 must be added to these addr

19AT90S/LS2323/23431004D–09/01• Bit 0 – C: Carry FlagThe carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-tion

2AT90S/LS2323/23431004D–09/01Description The AT90S/LS2323 and AT90S/LS2343 are low-power, CMOS, 8-bit microcontrollersbased on the AVR RISC architectu

20AT90S/LS2323/23431004D–09/01The most typical program setup for the Reset and Interrupt vector addresses are:Reset Sources The AT90S2323/2343 provide

21AT90S/LS2323/23431004D–09/01Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).Note: 1. The Power-on R

22AT90S/LS2323/23431004D–09/01Figure 25. MCU Start-up, RESET Tied to VCC.Figure 26. MCU Start-up, RESET Controlled ExternallyExternal Reset An exter

23AT90S/LS2323/23431004D–09/01Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycleduration. On the fa

24AT90S/LS2323/23431004D–09/01Interrupt Handling The AT90S2323/2343 has two 8-bit interrupt mask control registers; GIMSK (GeneralInterrupt Mask regis

25AT90S/LS2323/23431004D–09/01General Interrupt Flag Register – GIFR• Bit 7 – Res: Reserved BitThis bit is a reserved bit in the AT90S2323/2343 and al

26AT90S/LS2323/23431004D–09/01• Bit 0 – Res: Reserved BitThis bit is a reserved bit in the AT90S2323/2343 and always reads zero.External Interrupt The

27AT90S/LS2323/23431004D–09/01activate the interrupt are defined in Table 9. The value on the INT01 pin is sampledbefore detecting edges. If edge or t

28AT90S/LS2323/23431004D–09/01Timer/Counter The AT90S2323/2343 provides one general-purpose 8-bit Timer/Counter –Timer/Counter0. The Timer/Counter has

29AT90S/LS2323/23431004D–09/01Figure 30. Timer/Counter 0 Block DiagramTimer/Counter0 Control Register – TCCR0• Bits 7..3 – Res: Reserved BitsThese bi

3AT90S/LS2323/23431004D–09/01Figure 2. The AT90S/LS2323 Block DiagramThe AT90S2323/2343 provides the following features: 2K bytes of In-System Progra

30AT90S/LS2323/23431004D–09/01The Stop condition provides a Timer Enable/Disable function. The CK down dividedmodes are scaled directly from the CK os

31AT90S/LS2323/23431004D–09/01Watchdog Timer Control Register – WDTCR• Bits 7..5 – Res: Reserved BitsThese bits are reserved bits in the AT90S2323/234

32AT90S/LS2323/23431004D–09/01EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the rang

33AT90S/LS2323/23431004D–09/01EEPROM Control Register – EECR• Bits 7..3 – Res: Reserved BitsThese bits are reserved bits in the AT90S2323/2343 and wil

34AT90S/LS2323/23431004D–09/01Prevent EEPROM CorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too

35AT90S/LS2323/23431004D–09/01I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/Oports. This means tha

36AT90S/LS2323/23431004D–09/01Port B Input Pins Address – PINBThe Port B Input Pins address (PINB) is not a register and this address enables accessto

37AT90S/LS2323/23431004D–09/01Memory ProgrammingProgram and Data Memory Lock BitsThe AT90S2323/2343 MCU provides two Lock bits that can be left unprog

38AT90S/LS2323/23431004D–09/013. $002: $03 (indicates AT90S/LS2343 when signature byte $001 is $91)Note: When both Lock bits are programmed (Lock mode

39AT90S/LS2323/23431004D–09/01High-voltage Serial Programming AlgorithmTo program and verify the AT90S/LS2323 and AT90S/LS234 in the high-voltage Seri

4AT90S/LS2323/23431004D–09/01chip, the Atmel AT90S2323/2343 is a powerful microcontroller that provides a highlyflexible and cost-effective solution t

40AT90S/LS2323/23431004D–09/01Table 16. High-voltage Serial Programming Instruction SetInstructionInstruction FormatOperation RemarksInstr.1 Instr.2

41AT90S/LS2323/23431004D–09/01Note: a = address high bitsb = address low bitsi = data ino = data outx = don’t care1 = Lock Bit12 = Lock Bit2F = FSTRT

42AT90S/LS2323/23431004D–09/01High-voltage Serial Programming CharacteristicsFigure 34. High-voltage Serial Programming TimingLow-voltage Serial Down

43AT90S/LS2323/23431004D–09/01For the EEPROM, an auto-erase cycle is provided within the self-timed Write instructionand there is no need to first exe

44AT90S/LS2323/23431004D–09/017. At the end of the programming session, RESET can be set high to commence normal operation.8. Power-off sequence (if n

45AT90S/LS2323/23431004D–09/01Notes: 1. a = address high bitsb = address low bitsH = 0 – Low byte, 1 – High byteo = data outi = data inx = don’t care1

46AT90S/LS2323/23431004D–09/01Low-voltage Serial Programming CharacteristicsFigure 37. Low-voltage Serial Programming TimingTable 20. Low-voltage Se

47AT90S/LS2323/23431004D–09/01Electrical CharacteristicsNotes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.2. “Min”

48AT90S/LS2323/23431004D–09/01External Clock Drive WaveformsFigure 38. WaveformsExternal Clock DriveTA = -40°C to 85°CSymbol ParameterVCC: 2.7V to 4.

49AT90S/LS2323/23431004D–09/01Typical CharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. A

5AT90S/LS2323/23431004D–09/01Pin Descriptions AT90S/LS2343VCC Supply voltage pin.GND Ground pin.Port B (PB4..PB0) Port B is a 5-bit bi-directional I/O

50AT90S/LS2323/23431004D–09/01Figure 40. Active Supply Current vs. VCCFigure 41. Active Supply Current vs. VCC0123456789102 2.5 3 3.5 4 4.5 5 5.5 6A

51AT90S/LS2323/23431004D–09/01Figure 42. Idle Supply Current vs. FrequencyFigure 43. Idle Supply Current vs. VCC00.511.522.533.544.550 1 2 3 4 5 6 7

52AT90S/LS2323/23431004D–09/01Figure 44. Idle Supply Current vs. VCCFigure 45. Power-down Supply Current vs. VCC00.10.20.30.40.50.60.70.82 2.5 3 3.5

53AT90S/LS2323/23431004D–09/01Figure 46. Power-down Supply Current vs. VCCFigure 47. Watchdog Oscillator Frequency vs. VCC0204060801001201401601802

54AT90S/LS2323/23431004D–09/01Note: Sink and source capabilities of I/O ports are measured on one pin at a time.Figure 48. Pull-up Resistor Current v

55AT90S/LS2323/23431004D–09/01Figure 50. I/O Pin Sink Current vs. Output VoltageFigure 51. I/O PIn Source Current vs. Output Voltage0102030405060700

56AT90S/LS2323/23431004D–09/01Figure 52. I/O Pin Sink Current vs. Output VoltageFigure 53. I/O Pin Source Current vs. Output voltage05101520250 0.5

57AT90S/LS2323/23431004D–09/01Figure 54. I/O Pin Input Threshold Voltage vs. VCCFigure 55. I/O Pin Input Hysteresis vs. VCC00.511.522.52.7 4.0 5.0Th

58AT90S/LS2323/23431004D–09/01Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory

59AT90S/LS2323/23431004D–09/01 Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, R

6AT90S/LS2323/23431004D–09/01Figure 4. External Clock Drive ConfigurationGNDGNDEXTERNALOSCILATORSIGNALEXTERNALOSCILATORSIGNALNCXTAL2XTAL1PB3AT90S/LS2

60AT90S/LS2323/23431004D–09/01DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move between Registers Rd ← Rr None 1LDI Rd, K Load Immediate Rd ← K None 1LD Rd, X

61AT90S/LS2323/23431004D–09/01Notes: 1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The inter

62AT90S/LS2323/23431004D–09/01Packaging Information8P310.16(0.400)9.017(0.355)PIN17.11(0.280)6.10(0.240).300 (7.62) REF5.33(0.210) MAX254(0.100) BSC 0

63AT90S/LS2323/23431004D–09/018S2.020 (.508).012 (.305).213 (5.41).205 (5.21).330 (8.38).300 (7.62)PIN 1 .050 (1.27) BSC.212 (5.38).203 (5.16).080 (2.

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

7AT90S/LS2323/23431004D–09/01Architectural OverviewThe fast-access register file concept contains 32 x 8-bit general-purpose working regis-ters with a

8AT90S/LS2323/23431004D–09/01The AVR has Harvard architecture – with separate memories and buses for programand data. The program memory is accessed w

9AT90S/LS2323/23431004D–09/01General-purpose Register FileFigure 7 shows the structure of the 32 general-purpose registers in the CPU.Figure 7. AVR C