
ii
ATtiny2313
2543A–AVR–08/03
Timed Sequences for Changing the Configuration of the Watchdog Timer ....... 44
Interrupts............................................................................................. 45
Interrupt Vectors in ATtiny2313 .......................................................................... 45
I/O-Ports............................................................................................... 47
Introduction......................................................................................................... 47
Ports as General Digital I/O................................................................................ 48
Alternate Port Functions ..................................................................................... 52
Register Description for I/O-Ports....................................................................... 60
External Interrupts.............................................................................. 61
8-bit Timer/Counter0 with PWM......................................................... 64
Overview............................................................................................................. 64
Timer/Counter Clock Sources............................................................................. 65
Counter Unit........................................................................................................ 65
Output Compare Unit.......................................................................................... 66
Compare Match Output Unit............................................................................... 68
Modes of Operation ............................................................................................ 69
Timer/Counter Timing Diagrams......................................................................... 73
8-bit Timer/Counter Register Description ........................................................... 75
Timer/Counter0 and Timer/Counter1 Prescalers ............................. 81
16-bit Timer/Counter1 ........................................................................ 83
Overview............................................................................................................. 83
Accessing 16-bit Registers ................................................................................. 86
Timer/Counter Clock Sources............................................................................. 89
Counter Unit........................................................................................................ 89
Input Capture Unit............................................................................................... 90
Output Compare Units ........................................................................................ 92
Compare Match Output Unit............................................................................... 94
Modes of Operation ............................................................................................ 95
Timer/Counter Timing Diagrams....................................................................... 103
16-bit Timer/Counter Register Description ....................................................... 105
USART ............................................................................................... 113
Overview........................................................................................................... 113
Clock Generation.............................................................................................. 114
Frame Formats ................................................................................................. 117
USART Initialization.......................................................................................... 118
Data Transmission – The USART Transmitter ................................................. 120
Data Reception – The USART Receiver .......................................................... 123
Asynchronous Data Reception ......................................................................... 126
Multi-processor Communication Mode ............................................................. 130
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