Rainbow-electronics AT90C8534 Bedienungsanleitung

1Features• Utilizes the AVR® RISC Architecture• AVR – High-performance and Low-power RISC Architecture– 118 Powerful Instructions – Most Single Clock

AT90C853410I/O DirectFigure 11. I/O Direct AddressingOperand address is contained in six bits of the instruction word. n is the destination or source

AT90C853411Data Indirect with DisplacementFigure 13. Data Indirect with DisplacementOperand address is the result of the Y- or Z-register contents ad

AT90C853412Data Indirect with Pre-decrementFigure 15. Data Indirect Addressing with Pre-decrementThe X-, Y- or the Z-register is decremented before t

AT90C853413Constant Addressing Using the LPM InstructionFigure 17. Code Memory Constant AddressingConstant byte address is specified by the Z-registe

AT90C853414Relative Program Addressing, RJMP And RCALLFigure 19. Relative Program Memory AddressingProgram execution continues at address PC + k + 1.

AT90C853415Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two registeroperands is e

AT90C853416I/O MemoryThe I/O space definition of the AT90C8534 is shown in Table 1.Note: Reserved and unused locations are not shown in the table.The

AT90C853417Status Register – SREGThe AVR status register (SREG) at I/O space location $3F ($5F) is defined as:•Bit 7 – I: Global Interrupt EnableThe g

AT90C853418decremented by 2 when data is pushed onto the stack with subroutine RCALL and interrupt. The Stack Pointer is incre-mented by 1 when data i

AT90C853419ResetDuring reset, all I/O registers are set to their initial values and the program counter is set to address $000. When reset isreleased,

AT90C85342AT90C8534 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consump-tion versus processing spee

AT90C853420Figure 24. External Reset on Start-upFigure 25. External Reset during OperationInterrupt HandlingThe AT90C8534 has two 8-bit Interrupt Ma

AT90C853421General Interrupt Mask Register – GIMSK•Bit 7 – INT1: External Interrupt Request 1 EnableWhen the INT1 bit is set (one) and the I-bit in th

AT90C853422Timer/Counter Interrupt Mask Register – TIMSK•Bits 7..3 – Res: Reserved BitsThese bits are reserved bits in the AT90C8534 and always read a

AT90C853423MCU Control Register – MCUCRThe MCU Control Register contains control bits for general MCU functions.•Bit 7 – Res: Reserved BitThis bit is

AT90C853424Power-down ModeWhen the SM bit is set (one), the SLEEP instruction makes the MCU enter the Power-down Mode. In this mode, theexternal oscil

AT90C853425Figure 27. Timer/Counter0 Block DiagramTimer/Counter0 Control Register – TCCR0•Bits 7..3 – Res: Reserved BitsThese bits are reserved bits

AT90C853426Timer Counter0 – TCNT0The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a cl

AT90C853427•Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Cou

AT90C853428EEPROM Read/Write AccessThe EEPROM access registers are accessible in the I/O space.The write access time is in the range of 2.5 - 35 ms, d

AT90C853429•Bit 1 – EEWE: EEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctl

AT90C85343The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directlyconnected to the Ar

AT90C853430Analog-to-digital ConverterFeature list:• 10-bit Resolution• ± 2 LSB Accuracy (AVcc = 3.3 - 6.0V)• 76 - 175 µs Conversion Time• Up to 13 kS

AT90C853431A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC. This bit stays high as long as theconversion is in

AT90C853432Figure 31. ADC Timing Diagram, First Conversion (Single Conversion Mode)Figure 32. ADC Timing Diagram, Single ConversionMSB of resultLSB

AT90C853433Figure 33. ADC Timing Diagram, Free Run ConversionADC Noise Canceler FunctionThe ADC features a noise canceler that enables conversion dur

AT90C853434ADC Multiplexer Select Register – ADMUX•Bits 7..3 – Res: Reserved BitsThese bits are reserved bits in the AT90C8534 and always read as zero

AT90C853435the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical “1” to the flag. Beware that ifdoing a rea

AT90C853436ADC Noise Canceling TechniquesDigital circuitry inside and outside the AT90C8534 generates EMI, which might affect the accuracy of analog m

AT90C853437Note: 1. AVCC must not go below 3.3V or above 6.0V.Output Port APort A is a 7-bit general output port with tri-state mode.The port has true

AT90C853438Note: n: 6, 5, …, 0, pin number.Memory ProgrammingProgram and Data Memory Lock BitsThe AT90C8534 MCU provides two Lock bits that can be lef

AT90C853439Signal NamesIn this section, some pins of the AT90C8534 are referenced by signal names describing their function during parallel pro-grammi

AT90C85344Crystal OscillatorsXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier that can be configured for use as an on-chi

AT90C853440.Enter Programming ModeThe following algorithm puts the device in parallel programming mode:1. Apply 5V between VCC and GND.2. Set PEN, RES

AT90C853441Programming the FlashA: Load Command “Write Flash”1. Set XA1, XA0 to “10”. This enables command loading.2. Set BS to “0”3. Set DATA to “000

AT90C853442Figure 36. Programming the Flash WaveformsFigure 37. Programming the Flash Waveforms (Continued)Reading the FlashThe algorithm for readin

AT90C853443Programming the EEPROMThe programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” for details onco

AT90C853444Parallel Programming CharacteristicsFigure 38. Parallel Programming TimingNotes: 1. Use tWLWH_CE for Chip Erase.2. If tWLWH is held longer

AT90C853445Electrical CharacteristicsNotes: 1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”).2. “Min” mean

AT90C853446External Clock Drive WaveformsFigure 39. External ClockExternal Clock DriveSymbol ParameterVCC = 3.3V to 6.0VUnitsMin Max1/tCLCLOscillator

AT90C853447Typical CharacteristicsThe following charts show typical behavior. These data are characterized, but not tested.Sink and source capabilitie

AT90C853448Figure 42. I/O Pin Sink Current vs. Output VoltageFigure 43. I/O Pin Source Current vs. Output VoltageI (mA)OLV (V)OLT = 85˚CAT = 25˚

AT90C853449Note: For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should neve

AT90C85345The I/O memory space contains 64 addresses for CPU peripheral functions such as Control Registers, Timer/Counters,A/D converters and other I

AT90C853450Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add Two Registers

AT90C853451DATA TRANSFER INSTRUCTIONSMOV Rd, Rr Move between Registers Rd ← Rr None 1LDI Rd, K Load Immediate Rd ← KNone1LD Rd, X Load Indirect Rd ← (

AT90C853452Ordering InformationSpeed (MHz) Power Supply Ordering Code Package Operation Range1.5 3.3 - 6.0V AT90C8534-1AC 48A Commercial(0°C to 70°C)1

AT90C853453Packaging Information*Controlling dimension: millimeters0.50(0.020) BSCPIN 1 ID0.20(.008)0.09(.003)0˚7˚0.15(0.006)0.05(0.002)0.75(0.030)0.4

© Atmel Corporation 2000.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa

AT90C85346Figure 5. Memory MapsA flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit

AT90C85347General-purpose Register FileFigure 6 shows the structure of the 32 general-purpose working registers in the CPU.Figure 6. AVR CPU General-

AT90C85348ALU – Arithmetic Logic UnitThe high-performance AVR ALU operates in direct connection with all the 32 general-purpose working registers. Wit

AT90C85349The Indirect with Displacement mode features 63 address locations reached from the base address given by the Y- orZ-register.When using regi