Rainbow-electronics AT90LS4433 Bedienungsanleitung

1Features• High-performance and Low-power AVR®8-bit RISC Architecture– 118 Powerful Instructions – Most Single Cycle Execution– 32x8GeneralPurposeWork

10AT90S/LS44331042G–AVR–09/02General PurposeRegister FileFigure 7 shows the structure of the 32 general purpose working registers in the CPU.Figure 7.

100AT90S/LS44331042G–AVR–09/02External Clock DriveWaveformsFigure 69. External ClockTable 39. External Clock DriveSymbol ParameterVCC=2.7Vto6.0V VCC=4

101AT90S/LS44331042G–AVR–09/02TypicalCharacteristicsThe following charts show typical behavior. These figures are not tested during manu-facturing. Al

102AT90S/LS44331042G–AVR–09/02Figure 71. Active Supply Current vs. VCCFigure 72. Idle Supply Current vs. Frequency024681012142 2.5 3 3.5 4 4.5 5 5.5 6

103AT90S/LS44331042G–AVR–09/02Figure 73. Idle Supply Current vs. VCCFigure 74. Power-down Supply Current vs. VCCTA = 25˚CTA = 85˚CIDLE SUPPLY CURRENT

104AT90S/LS44331042G–AVR–09/02Figure 75. Power-down Supply Current vs. VCCFigure 76. Power-down Supply Current vs. VCC0204060801001202 2.5 3 3.5 4 4.5

105AT90S/LS44331042G–AVR–09/02Figure 77. Analog Comparator Current vs. VCCAnalog Comparator offset voltage is measured as absolute offset.Figure 78. A

106AT90S/LS44331042G–AVR–09/02Figure 79. Analog Comparator Offset Voltage vs. Common Mode VoltageFigure 80. Analog Comparator Input Leakage Current024

107AT90S/LS44331042G–AVR–09/02Figure 81. Watchdog Oscillator Frequency vs. VCCSink and source capabilities of I/O ports are measured on one pin at a t

108AT90S/LS44331042G–AVR–09/02Figure 83. Pull-up Resistor Current vs. Input VoltageFigure 84. I/O Pin Sink Current vs. Output Voltage0510152025300 0.5

109AT90S/LS44331042G–AVR–09/02Figure 85. I/O Pin Source Current vs. Output VoltageFigure 86. I/O Pin Sink Current vs. Output Voltage0246810121416180 0

11AT90S/LS44331042G–AVR–09/02In the different addressing modes, these address registers have functions as fixed dis-placement, automatic increment and

110AT90S/LS44331042G–AVR–09/02Figure 87. I/O Pin Source Current vs. Output VoltageFigure 88. I/O Pin Input Threshold Voltage vs. VCC01234560 0.5 1 1.5

111AT90S/LS44331042G–AVR–09/02Figure 89. I/O Pin Input Hysteresis vs. VCC00.020.040.060.080.10.120.140.160.182.7 4.0 5.0Input Hysteresis (V)VCCI/O PIN

112AT90S/LS44331042G–AVR–09/02Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page$3F ($5F) SREG I T H S V N Z C page 19$

113AT90S/LS44331042G–AVR–09/02Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memor

114AT90S/LS44331042G–AVR–09/02Instruction Set SummaryMnemonic Operands Description Operation Flags # ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr

115AT90S/LS44331042G–AVR–09/02LD Rd, Y Load Indirect Rd ← (Y) None 2LD Rd, Y+ Load Indirect and Post-inc. Rd ← (Y), Y ← Y + 1 None 2LD Rd, -Y Load Ind

116AT90S/LS44331042G–AVR–09/02Ordering InformationPower Supply Speed (MHz) Ordering Code Package Operation Range2.7 - 6.0V 4 AT90LS4433-4ACAT90LS4433-

117AT90S/LS44331042G–AVR–09/02Packaging Information32A8.75 (0.344) 8.75 (0.344)0.45 (0.018)0.30 (0.012)PIN 1 ID0.80 (0.0315) BSC 6.90 (0.272)0.20 (0.0

118AT90S/LS44331042G–AVR–09/0228P334.80(1.370)34.54(1.360)8.26(0.325)7.62(0.300)10.20(0.400)MAX0.38(0.015)2.54(0.100)BSC3.56(0.140)3.05(0.120)4.57(0.1

119AT90S/LS44331042G–AVR–09/02Errata forAT90S/LS4433 Rev.Rev. C/D/E/F• Fuses and Programming Mode• Incorrect Channel Change in Free Running Mode• Band

12AT90S/LS44331042G–AVR–09/02The direct addressing reaches the entire data space. The Indirect with Displacementmode features 63 address locations rea

120AT90S/LS44331042G–AVR–09/021. UART Loses Synchronization if RXD Line is Low when UART Receive isDisabledThe UART will detect a UART start bit and s

121AT90S/LS44331042G–AVR–09/02Data SheetChange Log forAT90S/LS4433This section containes a log on the changes made to the data sheet for AT90S/LS4433.

122AT90S/LS44331042G–AVR–09/02

iAT90S/LS44331042G–AVR–09/02Table of ContentsFeatures...

iiAT90S/LS44331042G–AVR–09/02Prescaling ... 65

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contain

13AT90S/LS44331042G–AVR–09/02I/O Direct Figure 12. I/O Direct AddressingOperand address is contained in six bits of the instruction word. n is the des

14AT90S/LS44331042G–AVR–09/02Data Indirect Figure 15. Data Indirect AddressingOperand address is the contents of the X-, Y-, or the Z-register.Data In

15AT90S/LS44331042G–AVR–09/02Constant Addressing Usingthe LPM InstructionFigure 18. Code Memory Constant AddressingConstant byte address is specified

16AT90S/LS44331042G–AVR–09/02EEPROM Data Memory The AT90S4433 contains 256 bytes of data EEPROM memory. It is organized as a sep-arate data space, in

17AT90S/LS44331042G–AVR–09/02Figure 23. On-chip Data SRAM Access CyclesI/O Memory The I/O space definition of the AT90S4433 is shown in Table 2.System

18AT90S/LS44331042G–AVR–09/02Note: 1. Reserved and unused locations are not shown in the table.All AT90S4433 I/Os and peripherals are placed in the I/

19AT90S/LS44331042G–AVR–09/02Status Register – SREG The AVR Status Register (SREG) at I/O space location $3F ($5F) is defined as:• Bit 7 – I: Global I

2AT90S/LS44331042G–AVR–09/02Pin Configurations TQFP Top ViewPDIP123456782423222120191817(INT1) PD3(T0) PD4NCVCCGNDNCXTAL1XTAL2PC1 (ADC1)PC0 (ADC0)NCAG

20AT90S/LS44331042G–AVR–09/02Stack Pointer – SP The AT90S4433 Stack Pointer is implemented as an 8-bit register in the I/O space loca-tion $3D ($5D).

21AT90S/LS44331042G–AVR–09/02The most typical program setup for the Reset and Interrupt Vector addresses are:Address Labels Code Comments$000 rjmp RES

22AT90S/LS44331042G–AVR–09/02Figure 24. Reset LogicNote: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT(falling).Ta

23AT90S/LS44331042G–AVR–09/02Note: 1. Or external Power-on Reset.This table shows the Start-up times from Reset. From sleep, only the clock counting p

24AT90S/LS44331042G–AVR–09/02Figure 25. MCU Start-up, RESET Tied to VCCFigure 26. MCU Start-up, RESET Controlled ExternallyExternal Reset An External

25AT90S/LS44331042G–AVR–09/02Brown-out Detection AT90S4433 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCClevel during the ope

26AT90S/LS44331042G–AVR–09/02MCU Status Register –MCUSRThe MCU Status Register provides information on which reset source caused an MCUReset.• Bits 7.

27AT90S/LS44331042G–AVR–09/02Note that the Status Register is not automatically stored when entering an interrupt rou-tine or restored when returning

28AT90S/LS44331042G–AVR–09/02• Bit 6 – INTF0: External Interrupt Flag0When an edge on the INT0 pin triggers an interrupt request, the corresponding In

29AT90S/LS44331042G–AVR–09/02Timer/Counter Interrupt FlagRegister – TIFR• Bit 7 – TOV1: Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an over

3AT90S/LS44331042G–AVR–09/02Description The AT90S4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISCarchitecture. By executing powerf

30AT90S/LS44331042G–AVR–09/02External Interrupts The External Interrupts are triggered by the INT1 and INT0 pins. Observe that, ifenabled, the interru

31AT90S/LS44331042G–AVR–09/02• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0The External Interrupt 1 is activated by the externa

32AT90S/LS44331042G–AVR–09/02Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idlemode stopping the CPU but

33AT90S/LS44331042G–AVR–09/02Timer/Counters The AT90S4433 provides two general purpose Timer/Counters – one 8-bit T/C and one16-bit T/C. Timer/Counter

34AT90S/LS44331042G–AVR–09/02Figure 31. Timer/Counter0 Block DiagramTimer/Counter0 ControlRegister – TCCR0• Bits 7 – 3 – Res: Reserved BitsThese bits

35AT90S/LS44331042G–AVR–09/02The Stop condition provides a Timer Enable/Disable function. The prescaled CK modesare scaled directly from the CK Oscill

36AT90S/LS44331042G–AVR–09/02Interrupt Flag Register (TIFR). The interrupt enable/disable settings for Timer/Counter1are found in the Timer/Counter In

37AT90S/LS44331042G–AVR–09/02Timer/Counter1 ControlRegister A – TCCR1A• Bits 7, 6 – COM11, COM10: Compare Output Mode1, Bits 1, and 0The COM11 and COM

38AT90S/LS44331042G–AVR–09/02Timer/Counter1 ControlRegister B – TCCR1B• Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs)When the ICNC1 bit is clea

39AT90S/LS44331042G–AVR–09/02• Bits 2, 1, 0 – CS12, CS11, CS10: Clock Select1, Bits 2, 1, and 0The Clock Select1 bits 2, 1, and 0 define the prescalin

4AT90S/LS44331042G–AVR–09/02Block Diagram Figure 1. The AT90S4433 Block DiagramPROGRAMCOUNTERINTERNALOSCILLATORWATCHDOGTIMERSTACKPOINTERPROGRAMFLASHMC

40AT90S/LS44331042G–AVR–09/02the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for afull 16-bit register read operation.The

41AT90S/LS44331042G–AVR–09/02Timer/Counter1 Input CaptureRegister – ICR1H and ICR1LThe Input Capture Register is a 16-bit, read only register.When the

42AT90S/LS44331042G–AVR–09/02Note that in the PWM mode, the ten least significant OCR1 bits, when written, are trans-ferred to a temporary location. T

43AT90S/LS44331042G–AVR–09/02Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator. By controlling theWatchdog Timer prescal

44AT90S/LS44331042G–AVR–09/02• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0The WDP2, WDP1, and WDP0 bits determine the Watchdog

45AT90S/LS44331042G–AVR–09/02EEPROM Read/WriteAccessThe EEPROM Access Registers are accessible in the I/O space.The write access time is in the range

46AT90S/LS44331042G–AVR–09/02• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt

47AT90S/LS44331042G–AVR–09/02Prevent EEPROMCorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply volt-age is too lo

48AT90S/LS44331042G–AVR–09/02Serial PeripheralInterface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween

49AT90S/LS44331042G–AVR–09/02Figure 37. SPI Master-slave InterconnectionThe system is single buffered in the transmit direction and double buffered in

5AT90S/LS44331042G–AVR–09/02Pin DescriptionsVCC Supply voltage.GND Ground.Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pu

50AT90S/LS44331042G–AVR–09/02pins are inputs. When SS is driven high, externally all pins are inputs and the SPI ispassive, which means that it will n

51AT90S/LS44331042G–AVR–09/02SPIControlRegister– SPCR• Bit 7 – SPIE: SPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit

52AT90S/LS44331042G–AVR–09/02SPI Status Register – SPSR• Bit 7 – SPIF: SPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one)

53AT90S/LS44331042G–AVR–09/02UART The AT90S4433 features a full duplex (separate Receive and Transmit Registers) Uni-versal Asynchronous Receiver and

54AT90S/LS44331042G–AVR–09/02data is transferred from UDR to the 10(11)-bit Shift Register, bit 0 of the Shift Register iscleared (start bit) and bit

55AT90S/LS44331042G–AVR–09/02The Receiver front-end logic samples the signal on the RXD pin at a frequency 16 timesthe baud rate. While the line is id

56AT90S/LS44331042G–AVR–09/02Multi-processorCommunication ModeThe Multi-processor Communication mode enables several slave MCUs to receive datafrom a

57AT90S/LS44331042G–AVR–09/02UART ControlUART I/O Data Register – UDRThe UDR Register is actually two physically separate registers sharing the same I

58AT90S/LS44331042G–AVR–09/02• Bit 4 – FE: Framing ErrorThis bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-

59AT90S/LS44331042G–AVR–09/02• Bit 3 – TXEN: Transmitter EnableThis bit enables the UART Transmitter when set (one). When disabling the Transmitterwhi

6AT90S/LS44331042G–AVR–09/02Clock OptionsCrystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, whichcan be

60AT90S/LS44331042G–AVR–09/02Table 19. UBR Settings at Various Crystal FrequenciesBaud Rate1MHz%Error1.8432 MHz%Error2MHz%Error2.4576 MHz%Error2400UBR

61AT90S/LS44331042G–AVR–09/02UART Baud Rate Register –UBRRThis is a 12-bit register that contains the UART Baud Rate according to the equation onthe p

62AT90S/LS44331042G–AVR–09/02Analog Comparator The Analog Comparator compares the input values on the positive input PD6 (AIN0)and negative input PD7

63AT90S/LS44331042G–AVR–09/02• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set (one) when a comparator output event triggers the interrup

64AT90S/LS44331042G–AVR–09/02Analog-to-DigitalConverterFeatures • 10-bit Resolution• ±2 LSB Absolute Accuracy• 0.5 LSB Integral Non-linearity• 65 - 26

65AT90S/LS44331042G–AVR–09/02Operation The ADC can operate in two modes: Single Conversion and Free Run mode. In SingleConversion mode, each conversio

66AT90S/LS44331042G–AVR–09/02keeps running for as long as the ADEN bit is set and is continuously reset when ADENis low.When initiating a conversion b

67AT90S/LS44331042G–AVR–09/02Figure 47. ADC Timing Diagram, Single ConversionFigure 48. ADC Timing Diagram, Free Run ConversionADC Noise CancelerFunct

68AT90S/LS44331042G–AVR–09/02ADC Multiplexer SelectRegister – ADMUX• Bit 7 – Res: Reserved BitThis bit is a reserved bit in the AT90S4433, and should

69AT90S/LS44331042G–AVR–09/02• Bit 5 – ADFR: ADC Free Run SelectWhen this bit is set (one), the ADC operates in Free Run mode. In this mode, the ADCsa

7AT90S/LS44331042G–AVR–09/02ArchitecturalOverviewThe fast-access Register File concept contains 32 x 8-bit general purpose working reg-isters with a s

70AT90S/LS44331042G–AVR–09/02Scanning MultipleChannelsSince change of analog channel always is delayed until a conversion is finished, theFree Run mod

71AT90S/LS44331042G–AVR–09/02Notes: 1. Minimum for AVCC is 2.7V.2. Maximum for AVCC is 6.0V.ADC Characteristics TA=-40°Cto85°CSymbol Parameter Conditi

72AT90S/LS44331042G–AVR–09/02I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This means that

73AT90S/LS44331042G–AVR–09/02The Port B Input Pins address (PINB) is not a register; this address enables access tothe physical value on each Port B p

74AT90S/LS44331042G–AVR–09/02controlled by DDB2. When the pin is forced to be an input, the pull-up can still be con-trolled by the PORTB2 bit. See th

75AT90S/LS44331042G–AVR–09/02Figure 51. Port B Schematic Diagram (Pin PB1)Figure 52. Port B Schematic Diagram (Pin PB2)PB1DDB1PORTB1WP:WD:RL:RP:RD:WRI

76AT90S/LS44331042G–AVR–09/02Figure 53. Port B Schematic Diagram (Pin PB3)Figure 54. Port B Schematic Diagram (Pin PB4)DATA BUSDDQQRESETRESETCCWDWPRDM

77AT90S/LS44331042G–AVR–09/02Figure 55. Port B Schematic Diagram (Pin PB5)Port C Port C is a 6-bit bi-directional I/O port.Three I/O memory address lo

78AT90S/LS44331042G–AVR–09/02Port C Data Register – PORTCPort C Data Direction Register– DDRCPort C Input Pins Address –PINCThe Port C Input Pins addr

79AT90S/LS44331042G–AVR–09/02Port C Schematics Note that all port pins are synchronized. The synchronization latch is, however, notshown in the figure

8AT90S/LS44331042G–AVR–09/02The I/O memory space contains 64 addresses for CPU peripheral functions such asControl Registers, Timer/Counters, A/D Conv

80AT90S/LS44331042G–AVR–09/02Port D Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.Three I/O memory address locations are

81AT90S/LS44331042G–AVR–09/02Port D as General Digital I/O PDn, General I/O pin: The DDDn bit in the DDRD Register selects the direction of thispin. I

82AT90S/LS44331042G–AVR–09/02• TXD – Port D, Bit 1Transmit Data (Data Output pin for the UART). When the UART Transmitter is enabled,this pin is confi

83AT90S/LS44331042G–AVR–09/02Figure 58. Port D Schematic Diagram (Pin PD1)Figure 59. Port D Schematic Diagram (Pins PD2 and PD3)DATA BUSDDQQRESETRESET

84AT90S/LS44331042G–AVR–09/02Figure 60. Port D Schematic Diagram (Pins PD4 and PD5)Figure 61. Port D Schematic Diagram (Pins PD6 and PD7)WP:WD:RL:RP:R

85AT90S/LS44331042G–AVR–09/02MemoryProgrammingProgram and DataMemory Lock BitsThe AT90S4433 MCU provides two Lock bits, which can be left unprogrammed

86AT90S/LS44331042G–AVR–09/02Programming the Flashand EEPROMAtmel’s AT90S4433 offers 4K bytes of In-System Reprogrammable Flash Programmemory and 256

87AT90S/LS44331042G–AVR–09/02Enter Programming Mode The following algorithm puts the device in Parallel Programming mode:1. Apply supply voltage accor

88AT90S/LS44331042G–AVR–09/02Chip Erase The Chip Erase command will erase the Flash and EEPROM memories and the Lockbits. The Lock bits are not reset

89AT90S/LS44331042G–AVR–09/02G:WriteDataHighByte1. Set BS to “1”. This selects high data.2. Give WRa negative pulse. This starts programming of the da

9AT90S/LS44331042G–AVR–09/02Figure 6. AT90S4433 Memory MapsA flexible interrupt module has its control registers in the I/O space with an additionalGl

90AT90S/LS44331042G–AVR–09/02Figure 64. Programming the Flash Waveforms (Continued)Reading the Flash The algorithm for reading the Flash memory is as

91AT90S/LS44331042G–AVR–09/02Programming the Fuse Bits The algorithm for programming the Fuse bits is as follows (refer to “Programming theFlash” for

92AT90S/LS44331042G–AVR–09/02Reading the Signature Bytes The algorithm for reading the signature bytes is as follows (refer to “Programming theFlash”

93AT90S/LS44331042G–AVR–09/02Serial Downloading Both the Program and Data memory arrays can be programmed using the SPI bus whileRESETis pulled to GND

94AT90S/LS44331042G–AVR–09/02ing the third byte of the Programming Enable instruction. Whether or not theecho is correct, all four bytes of the instru

95AT90S/LS44331042G–AVR–09/02Data Polling Flash When a byte is being programmed into the Flash, reading the address location beingprogrammed will give

96AT90S/LS44331042G–AVR–09/02Note: 1. The signature bytes are not readable in lock mode 3, i.e., both Lock bits programmed.a = address high bitsb = ad

97AT90S/LS44331042G–AVR–09/02Serial ProgrammingCharacteristicsFigure 68. Serial Programming TimingTable 36. Serial Programming Characteristics, TA=-40

98AT90S/LS44331042G–AVR–09/02Electrical CharacteristicsAbsolute Maximum Ratings*Operating Temperature... -55°Cto+125°C*

99AT90S/LS44331042G–AVR–09/02Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low (logical “0”).2. “Min” means the lo