Rainbow-electronics ATmega103L Bedienungsanleitung PDF herunterladen (Seite 30)

ATmega603/103

Interrupt Handling

The ATmega603/103 has two dedicated 8-bit Interrupt Mask control registers; EIMSK - External Interrupt Mask register and

TIMSK - Timer/Counter Interrupt Mask register. In addition, other enable and mask bits can be found in the peripheral

control registers.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft-

ware can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI

- is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-

ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set

and remembered until the interrupt is enabled, or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt

flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is

active.

Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from

an interrupt routine. This must be handled by software.

External Interrupt Mask Register - EIMSK

•

Bits 7..4 - INT7 - INT4: External Interrupt Request 7-4 Enable

When an INT7- INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin

interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register - EICR defines whether the

external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

•

Bits 3..0 - INT3 - INT0: External Interrupt Request 3-0 Enable

When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin

interrupt is enabled. The external interrupts are always low level triggered interrupts. Activity on any of these pins will trig-

ger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

When enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.

External Interrupt Flag Register - EIFR

•

Bits 7..4 - INTF7 - INTF4: External Interrupt 7-4 Flags

When an event on the INT7 - INT4 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF4

becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT4 in EIMSK, are set (one), the

MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is

cleared by writing a logical one to it.

•

Bits 3..0 - Res: Reserved Bits

These bits are reserved bits in the ATmega603/103 and always read as zero.

Bit 7654 3 2 10

$39 ($59) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bit 7654 3 2 10

$38 ($58) INTF7 INTF6 INTF5 INTF4 - - - - EIFR

Read/Write R/W R/W R/W R/W R R R R

Initial value 0 0 0 0 0 0 0 0

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 125 126

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