Rainbow-electronics ATtiny28L Bedienungsanleitung PDF herunterladen (Seite 15)

ATtiny28L/V

1062E–10/01

Note: 1. Due to limited number of clock cycles in the start-up period, it is recommended that

ceramic resonator be used.

This table shows the start-up times from reset. From Power-down mode, only the clock

counting part of the start-up time is used. The Watchdog oscillator is used for timing the

real-time part of the start-up time. The number WDT oscillator cycles used for each

time-out is shown in Table 6.

The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section

“Typical Characteristics” on page 55.

The device is shipped with CKSEL = 0010.

Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-

tion level is nominally 1.4V. The POR is activated whenever V

is below the detection

level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-

ure in supply voltage.

The Power-on Reset (POR) circuit ensures that the device is reset from power-on.

Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-

mines the delay for which the device is kept in RESET after V

rise. The time-out

period of the delay counter can be defined by the user through the CKSEL fuses. The

different selections for the delay period are presented in Table 5. The RESET signal is

activated again, without any delay, when the V

decreases below detection level. See

Figure 16.

If the built-in start-up delay is sufficient, RESET

can be connected to VCC directly or via

an external pull-up resistor. By holding the RESET

pin low for a period after V

has

been applied, the Power-on Reset period can be extended. Refer to Figure 17 for a tim-

ing example of this.

0100 Internal RC Oscillator 6 CK

0011 Internal RC Oscillator 4.2 ms + 6 CK

0010 Internal RC Oscillator 67 ms + 6 CK

0001 External Clock 6 CK

0000 External Clock 4.2 ms + 6 CK

Table 6. Number of Watchdog Oscillator Cycles

Time-out Number of Cycles

4.2 ms 1K

67 ms 16K

Table 5. ATtiny28 Clock Options and Start-up Time (Continued)

CKSEL3..0 Clock Source Start-up Time at 2.7V

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 74 75

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