MAX1082/MAX1083
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 10-Bit ADCs with Internal Reference
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CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
connected to the MAX1082/MAX1083
’
s SCLK input.
2) The MAX1082/MAX1083
’
s CS pin is driven low by
the TMS320
’
s XF_ I/O port to enable data to be
clocked into the MAX1082/MAX1083
’
s DIN pin.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1082/MAX1083 to initiate a conversion and
place the device into normal operating mode. See
Table 3 to select the proper XXXXX bit values for your
specific application.
4) The MAX1082/MAX1083
’
s SSTRB output is moni-
tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the con-
version is in progress and data is ready to be
received from the device.
5) The TMS320 reads in 1 data bit on each of the next
16 rising edges of SCLK. These data bits represent
the 10 + 2-bit conversion result followed by 4 trailing
bits, which should be ignored.
6) Pull CS high to disable the MAX1082/MAX1083 until
the next conversion is initiated.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
from a straight line on an actual transfer function. This
straight line can be a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1082/MAX1083
are measured using the best straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Width
Aperture width (t
AW
) is the time the T/H circuit requires
to disconnect the hold capacitor from the input circuit
(for instance, to turn off the sampling bridge, and put
the T/H unit in hold mode).
(11 Seiten)
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