Rainbow-electronics MAX1446 Bedienungsanleitung PDF herunterladen (Seite 12)

MAX1446

10-Bit, 60Msps, +3.0V, Low-Power

ADC with Internal Reference

12 ______________________________________________________________________________________

Figure 6 also shows the relationship between the input

clock parameters and the valid output data.

Applications Information

Figure 7 shows a typical application circuit containing a

single-ended to differential converter. The internal refer-

ence provides a V

/2 output voltage for level shifting

purposes. The input is buffered and then split to a volt-

age follower and inverter. A lowpass filter follows the op

amps to suppress some of the wideband noise associ-

ated with high-speed op amps. The user may select the

ISO

and C

values to optimize the filter performance

to suit a particular application. For the application in

Figure 7, an R

ISO

of 50Ω is placed before the capaci-

tive load to prevent ringing and oscillation. The 22pF

capacitor acts as a small bypassing capacitor.

Using Transformer Coupling

An RF transformer (Figure 8) provides an excellent

solution for converting a single-ended source signal to

a fully differential signal, required by the MAX1446 for

optimum performance. Connecting the transformer’s

center tap to COM provides a V

/2 DC level shift to

20 4030 50 60 70

CLOCK DUTY CYCLE (%)

SFDR (dBc)

= 12.5MHz AT -0.5dBFS

Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input)

20 4030 50 60 70

CLOCK DUTY CYCLE (%)

SNR (dB)

= 12.5MHz AT -0.5dBFS

Figure 3b. SNR vs. Clock Duty Cycle (Differential Input)

-40

-50

-60

-70

-80

20 4030 50 60 70

CLOCK DUTY CYCLE (%)

THD (dBc)

= 12.5MHz AT -0.5dBFS

Figure 4a. THD vs. Clock Duty Cycle (Differential Input)

20 4030 50 60 70

CLOCK DUTY CYCLE (%)

SINAD (dB)

= 12.5MHz AT -0.5dBFS

Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input)

1 2 ... 7 8 9 10 11 12 13 14 15 16

ADC with Internal Reference 1

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