MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
12 ______________________________________________________________________________________
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal refer-
ence provides a V
DD
/2 output voltage for level shifting
purposes. The input is buffered and then split to a volt-
age follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associ-
ated with high-speed op amps. The user may select the
R
ISO
and C
IN
values to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an RISO of 50Ω is placed before the capaci-
tive load to prevent ringing and oscillation. The 22pF
C
IN
capacitor acts as a small bypassing capacitor.
Kommentare zu diesen Handbüchern