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Rev. A – 31-May-01

This errata sheet describes the functional deviations known at the release date of this

document.

Errata History

Trouble descriptions

Lot Number Trouble list Status

All

T01, T02, T03, T04, T05, T06, T07, T08, T09, T10, T11,

T12, T13

Not Fixed

T01

During UART reception, clearing REN may generate unexpected IT.

Description

During Uart reception, if the REN bit is cleared between a start bit detection and the

end of reception, the Uart will not discard the data (RI is set).

Workaround

Test REN at the beginning of Interrupt routine just after CLR RI, and to run the

Interrupt routine code only if REN is set.

T02

Double IT on external falling edge on INT1 or INT0 in X2 Mode

Description

When CPU is in X2 mode and Timer1 or Timer 0 in X1 mode (CKCON = 0x7F), IEx

flag is not cleared by hardware after servicing interrupt. In this case, the CPU

executes the ISR a second time.

Workaround

The work around is to clear IEx bit in Interrupt subroutine.

INT1_ISR : ; Interrupt sub routine

CLR IE1

....

T03

Internal Resistor on Reset Pin

Description

Deviation from electrical specification. Typical value for internal resistor on Reset pin:

20K Ohms

Workaround

80C51 MCUs

T89C51RB2

T89C51RC2

Errata Sheet

1 2 3 4

Inhaltsverzeichnis

Seite 1 - Errata Sheet

Rev. A – 31-May-011This errata sheet describes the functional deviations known at the release date of thisdocument.Errata HistoryTrouble descriptionsL

Seite 2 - T89C51RB2/RC2

2T89C51RB2/RC2Rev. A – 31-May-01T04Bootloader - Write Page API - V1.1DescriptionThe Write Page API does not work correctly with the full page size.Wor

Seite 3

3T89C51RB2/RC2Rev. A – 31-May-01T10SPI interface - Spi SS pin Limitation on Master/SlaveDescriptionThe SS pin of the Spi was not got back as an I/O wh

Seite 4

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Rainbow-electronics T89C51RC2 Bedienungsanleitung

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