
Preliminary W78C52D
Publication Release Date: December 1998
- 11 - Revision A1
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Operating Speed FOP 0 - 24 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 10 - - nS 3
Clock Low TCL 10 - - nS 3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Address Valid to ALE Low TAAS
1 TCP-∆
--nS4
Address Hold from ALE Low TAAH
1 TCP-∆
- - nS 1, 4
ALE Low to PSEN Low
T
APL
1 TCP-∆
--nS4
PSEN Low to Data Valid
T
PDA --2 TCP nS 2
Data Hold after PSEN High
T
PDH 0 -1 TCP nS 3
Data Float after PSEN High
T
PDZ 0 -1 TCP nS
ALE Pulse Width TALW
2 TCP-∆
2 T
CP - nS 4
PSEN Pulse Width
T
PSW
3 TCP-∆
3 T
CP -nS4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP.
3. Data have been latched internally prior to
PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
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