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W78C54

8-BIT MICROCONTROLLER

Publication Release Date: December 1997

- 1 - Revision A2

GENERAL DESCRIPTION

The W78C54 is a derivative of the W78C52 microcontroller family that provides extended internal

ROM. The chip has 16K bytes of mask ROM and 256 bytes of RAM.

This device provides an enhanced architecture that makes it more powerful and suitable for a variety

of applications for general control systems. It provides on-chip 16KB mask ROM to accommodate

large program codes, 256-bytes of non-volatile on-chip RAM, four 8-bit I/O ports, one 4-bit I/O port,

three 16-bit timer/counters, eight sources with two-level interrupt structures, and on-chip oscillator

clock circuits.

FEATURES

• DC to 40 MHz extensive operating frequency

• 256-byte on-chip scratch pad RAM

• 16K-byte on-chip mask ROM

• 64K-byte address space for external Program Memory

• 64K-byte address space for external Data Memory

• Three 16-bit timer/counters

•

Four 8-bit bit-addressable I/O ports

• One extra 4-bit bit-addressable I/O port, additional INT2/ INT3

(Available on 44-pin PLCC/QFP package)

• Eight-source, two priority-level interrupts

• Low EMI emission mode

• Built-in programmable power-saving modes - Idle mode & Power-down mode

• Packages:

− DIP 40: W78C54-16/24/40

− PLCC 44: W78C54P-16/24/40

− QFP 44: W78C54F-16/24/40

− TQFP 44: W78C54M-16/24/40

1 2 3 4 5 6 ... 15 16

Inhaltsverzeichnis

Seite 1 - 8-BIT MICROCONTROLLER

W78C548-BIT MICROCONTROLLERPublication Release Date: December 1997 - 1 - Revision A2GENERAL DESCRIPTIONThe W78C54 is a derivative of the W78C52 mic

Seite 2 - PIN CONFIGURATIONS

W78C54- 10 -Following tables show the interrupt informations and priority definitions.Eight-source interrupt informations:INTERRUPTSOURCEVECTORADDRESS

Seite 3 - PIN DESCRIPTION

W78C54Publication Release Date: December 1997- 11 - Revision A2TR1: Timer 1 run control bit. Set/cleared by software to turn timer/counter on or off.T

Seite 4 - BLOCK DIAGRAM

W78C54- 12 -ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL MIN. MAX. UNITDC Power Supply VCC−VSS -0.3 +7.0 VInput Voltage VIN VSS -0.3 VCC +0.3 VOperating T

Seite 5 - W78C54 is used

W78C54Publication Release Date: December 1997- 13 - Revision A2DC Characteristics, continuedPARAMETER SYM. SPECIFICATION UNIT TEST CONDITIONSMIN. MAX

Seite 6 - Timers 0, 1, and 2

W78C54- 14 -Clock Input WaveformTTXTAL1FCHCLOP, TCPContinuedPARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTESOperating Speed FOP 0 - 40 MHz 1Clock Period TCP

Seite 7 - - 7 - Revision A2

W78C54Publication Release Date: December 1997- 15 - Revision A2Data Read CycleExternal Data Memory Read Cycle (see Figure 7)PARAMETER SYMBOL MIN. TYP.

Seite 8 - Power-off Flag

Seite 9 - SFR but in XICON

W78C54- 2 -PIN CONFIGURATIONSVCC12345678910111213141516171819203940343536373830313233262728292122232425P0.0, AD0P0.1, AD1P0.2, AD2P0.3, AD3P0.4, AD4P0

Seite 10 - *Timer/Counter

W78C54Publication Release Date: December 1997- 3 - Revision A2PIN DESCRIPTIONSYMBOL TYPE DESCRIPTIONSEA I EXTERNAL ACCESS ENABLE: This pin forces the

Seite 11 - *Reduced EMI Mode

W78C54- 4 -BLOCK DIAGRAMP3.0 ~P3.7P1.0 ~P1.7ALUPort 0LatchPort 1LatchTimer1Timer0Timer2Port1UARTXTAL1 PSENALE GNDVCCRSTXTAL2OscillatorInterruptPSW16

Seite 12 - DC CHARACTERISTICS

W78C54Publication Release Date: December 1997- 5 - Revision A2FUNCTIONAL DESCRIPTIONThe W78C54 is pin-to-pin compatible with the W78C52, except that t

Seite 13 - AC CHARACTERISTICS

W78C54- 6 -1. INT2 / INT3Two additional external interrupts, INT2 and INT3, whose functions are similar to those of externalinterrupt 0 and 1 in the s

Seite 14 - Program Fetch Cycle

W78C54Publication Release Date: December 1997- 7 - Revision A2DESCRIPTIONS OF THE SPECIAL FUNCTION REGISTERS (SFRS)SYM. DEFINITIONADDR. MSB

Seite 15 - Data Read Cycle

W78C54- 8 -Note: In column BIT_ADDRESS, SYMBOL, containing ( ) item means the bit address. * SFRs modified or added to the W78C52. + Reset value de

Seite 16

W78C54Publication Release Date: December 1997- 9 - Revision A2* Interrupts***IE - Interrupt Enable (A8H)EA - ET2 ES ET1 EX1 ET0 EX0EA: Lobal interrup

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