Rainbow-electronics ATF1504ASVL Bedienungsanleitung PDF herunterladen (Seite 15)

ATF1504ASV(L)

1409H–PLD–09/02

Power-down Mode The ATF1504ASV(L)includes an optional pin-controlledpower-down feature. Whenthis

mode is enabled, thePDpin acts as the power-down pin. WhenthePDpin is high, the

device supply current is reducedtoless than 3 mA.During power down, all output data

and internal logic statesare latchedinternally and held. Therefore,allregistered and

combinatorial output data remain valid. Any outputs that were in a High-Z state at the

onset will remain at High-Z.During power down, all input signals except the power-down

pin are blocked. Input and I/O hold latchesremain active to ensure that pins do not float

to indeterminate levels, furtherreducing systempower. The power-down mode feature

is enabledinthe logic design file or as a fittedortranslateds/woption.Designs using

the power-down pin may not use thePDpin as a logic array input.However, all other PD

pin macrocell resourcesmaystillbe used, including the buriedfeedback and foldback

product term array inputs.

Notes: 1. For slow slew outputs, add t

SSO

2. Pin or product term.

3. Includest

RPA

for reduced-powerbitenabled.

Power Down AC Characteristics

(1)(2)

Symbol Parameter

-15 -20

UnitsMin Max Min Max

IVDH

Valid I, I/ObeforePDHigh 15 20 ns

GVDH

Valid OE

(2)

beforePDHigh 15 20 ns

CVDH

Valid Clock

(2)

beforePDHigh 15 20 ns

DHIX

I, I/O Don’tCare after PD High 2530 ns

DHGX

(2)

Don’tCare after PD High 2530 ns

DHCX

Clock

(2)

Don’tCare after PD High 2530 ns

DLIV

PD Low to Valid I, I/O 11µs

DLGV

PD Low to Valid OE (Pin or Term) 11µs

DLCV

PD Low to Valid Clock (Pin or Term) 11µs

DLOV

PD Low to Valid Output 11µs

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 28 29

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