
7
AT77C105A [Preliminary]
5419A–BIOM–01/05
VDD_IO = 2.3V to 3.6V
Input/Output Voltage Level Compatibility
The I/O voltage level compatibility is set by the power voltage driven on the VDD_IO
pad. For 1.8V level compatibility, connect VDD_IO to a 1.8V power supply.
Table 10. Digital Inputs
Logic Compatibility CMOS
Name Parameter Conditions Test Level Min Typ Max Unit
I
IL
Low level input current without pull-
up device
(1)
V
I
= 0V I 1 µA
I
IH
High level input current without
pull-down device
(1)
V
I
= V
DD_IO
I1µA
I
IOZ
Tri-state output leakage without
pull-up/down device
(1)
V
I
= 0V or V
DD_IO
IV 1 µA
V
IL
Low level input voltage
(1)
I
0.5
V
DD_IO
(1)
V
V
IH
High level input voltage
(1)
I
0.6
V
DD_IO
(1)
V
V
HYST
Schmitt trigger hysteresis
(1)
IV
0.06
V
DD_IO
0.09
V
DD_IO
V
Table 11. Digital Outputs
Logic Compatibility CMOS
Name Parameter Conditions Test Level Min Typ Max Unit
V
OL
Low level output voltage
I
OL
= 4 mA
V
DD _IO
= 2.3V to
3.6V
I
0.10
V
DD_IO
(1)
V
V
OH
High level output voltage
I
OH
= -4 mA
V
DD_IO
= 2.3V to
3.6V
I0.90 V
DD
V
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