Rainbow-electronics MAX6948B Bedienungsanleitung PDF herunterladen (Seite 5)

High-Efficiency PWM LED Driver with Boost

Converter and Five Constant-Current GPIO Ports

MAX6948B

TIMING CHARACTERISTICS

(Typical Application Circuit, V+ = 2.7V to 5.0V, V

= 1.7V to V+, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

V+ = 3.3V, V

= 2.5V, T

= +25NC.) (Note 4)

Note 4: All parameters are tested at T

= +25NC. Specifications over temperature are guaranteed by design.

Note 5: The DI

PORT_

specifies current matching between ports of a single part.

Note 6: Current matching is defined as the percent error of any individual port from the average current of the maximum value

measured and the minimum value measured. It can be found using the equation DI

PORT_

= 100 x (I

MMAVG

- I

MEAS

MMAVG

where I

MMAVG

= (I

MEASMAX

+ I

MEASMIN

)/2.

Note 7: Guaranteed by design.

Note 8: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V

of the SCL signal) to

bridge the undefined region of SCL’s falling edge.

Note 9: I

SINK

P 6mA. C

= total capacitance of one bus line in pF. t

and t

are measured between 0.3 x V

and 0.7 x V

Note 10: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Internal Boost-Converter PWM

Clock Frequency

INT_

BOOST

98 125 145 kHz

Internal GPIO PWM Clock

Frequency

INT_GPIO

24 31.25 38 kHz

SCL Serial-Clock Frequency f

SCL

400 kHz

Bus Free Time Between a STOP

and START Condition

BUF

1.3

Hold Time (Repeated) START

Condition

HD, STA

0.6

Repeated START Condition Setup

Time

SU, STA

0.6

STOP Condition Setup Time t

SU, STO

0.6

Data Hold Time t

HD, DAT

(Note 8) 0.9

Data Setup Time t

SU, DAT

180 ns

SCL Clock Low Period t

LOW

1.3

SCL Clock High Period t

HIGH

0.7

Rise Time of Both SDA and SCL

Signals, Receiving

(Notes 7, 9)

20 +

0.1C

300 ns

Fall Time of Both SDA and SCL

Signals, Receiving

(Notes 7, 9)

20 +

0.1C

300 ns

Fall Time of SDA Transmitting t

F, TX

(Notes 7, 9)

20 +

0.1C

250 ns

Pulse Width of Spike Suppressed t

(Notes 7, 10) 50 ns

Serial Bus Timeout t

OUT

20 30 50 ms

Capacitive Load for Each Bus

Line

(Note 7) 400 pF

RST Pulse Width

1 2 3 4 5 6 7 8 9 10 ... 27 28

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