Rainbow-electronics T89C5121 Bedienungsanleitung

Rev. 4164G–SCR–07/06 Features• 80C51 Core– 12 or 6 Clocks per Instruction (X1 and X2 Modes)– 256 Bytes Scratchpad RAM– Dual Data Pointer– Two 16-bit

10 A/T8xC51214164G–SCR–07/06Port Structure DescriptionThe different ports structures are described as follows.Quasi Bi-directional Output Configurati

100 A/T8xC51214164G–SCR–07/06Table 73. Serial Interface DC parameters (P3.0, P3.1, P3.3 and P3.4)Table 74. LED outputs DC Parameters (P3.6 and P3.7

101A/T8xC51214164G–SCR–07/06Table 75. Smart Card 5V Interface DC ParametersNote: 1. Capacitor = 10 µF, X7R type. Maximum ESR value is 250 mohm, Indu

102 A/T8xC51214164G–SCR–07/06Table 78. Smart Card Clock DC Parameters (Port P1.4)Note: 1. The voltage on CLK should remain between -0.3V and CVCC +

103A/T8xC51214164G–SCR–07/06Table 80. Smart Card I/O DC Parameters (P1.0)Note: 1. The voltage on RST should remain between -0.3V and CVCC + 0.3V duri

104 A/T8xC51214164G–SCR–07/06Table 82. Smart Card RST, CC4, CC8, DC Parameters (Port P1.5, P1.3, P1.1) Note: 1. The voltage on RST should remain bet

105A/T8xC51214164G–SCR–07/06Typical ApplicationFigure 54. Typical Application DiagramNotes: 1. C4 and C5 must be placed near IC and have low ESR (<

106 A/T8xC51214164G–SCR–07/066. Distance between Device pads and Smart Card connector must be less than 4centimeters.7. C6,C7 should be as close as p

107A/T8xC51214164G–SCR–07/06Ordering InformationNote: 1. Contact Atmel for availability.Part NumberCode Memory Size (Bytes) Supply VoltageTemperature

108 A/T8xC51214164G–SCR–07/06Package DrawingsSSOP24

109A/T8xC51214164G–SCR–07/06PLCC52

11A/T8xC51214164G–SCR–07/06Figure 6. Push-pull Output ConfigurationLED Output Configuration The input only configuration is shown in Figure 7.Figure

110 A/T8xC51214164G–SCR–07/06QFN32

111A/T8xC51214164G–SCR–07/06Document Revision History for T8xC5121Changes from 4164B -06/02 to 4164C - 07/031. Ports description update.2. Added Bootl

i4164G–SCR–07/06A/T8xC5121Table of ContentsFeatures ...

ii4164G–SCR–07/06A/T8xC5121Memory Management ... 60Program Memory...

iii4164G–SCR–07/06A/T8xC5121Changes from 4164E - 01/04 to 4164F 11/05 ... 111Changes from 4164F 11/05 t

Printed on recycled paper.4164G–SCR–07/06© Atmel Corporation 2006. All rights reserved. Atmel®, logo and combinations thereof, are registered tradema

12 A/T8xC51214164G–SCR–07/06SFR Mapping The Special Function Registers (SFR) of the T8xC5121 belongs to the followingcategories:• C51 core registers:

13A/T8xC51214164G–SCR–07/06Reserved Table 2. SFR Addresses and Reset Values0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/FF8hFFhF0h B0000 0000LEDCONXXXX 0000F7hE8

14 A/T8xC51214164G–SCR–07/06PowerMonitor The PowerMonitor function supervises the evolution of the voltages feeding the micro-controller, and if need

15A/T8xC51214164G–SCR–07/06Figure 9. Power-Up and Steady-state Conditions MonitoredSuch device when it is integrated in a microcontroller, forces the

16 A/T8xC51214164G–SCR–07/06Power Monitoring and Clock ManagementFor applications where power consumption is a critical factor, three power modes are

17A/T8xC51214164G–SCR–07/06The ports status under Power-down is the status which was valid before entering thismode.The INT1 interrupt is a multiplexe

18 A/T8xC51214164G–SCR–07/06Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used withexternal program or

19A/T8xC51214164G–SCR–07/06Table 4. AUXR RegisterAUXR (S:8Eh)Auxiliary Register Reset Value = 00XX XX00b 76543210- LP - - - - EXTRAM AOBit Numb

2 A/T8xC51214164G–SCR–07/06Description T8xC5121 is a high performance CMOS ROM/CRAM derivative of the 80C51 CMOSsingle chip 8-bit microcontrollers. T

20 A/T8xC51214164G–SCR–07/06Table 5. IE0 RegisterIE0 Interrupt Enable Register (A8h)Reset Value = 0XX0 0000b76543210EA - - ES ET1 EX1 ET0 EX0Bit Num

21A/T8xC51214164G–SCR–07/06Table 6. ISEL RegisterISEL (S:BAh)Interrupt Enable RegisterReset Value = 0X00 0000b76543210CPLEV - RXIT PRESIT OELEV OEEN

22 A/T8xC51214164G–SCR–07/06Clock Management In order to optimize the power consumption and the execution time needed for a specifictask, an interna

23A/T8xC51214164G–SCR–07/06X2 Feature The T8xC5121 core needs only 6 clock periods per machine cycle. This feature called”X2” provides the following

24 A/T8xC51214164G–SCR–07/06Clock Prescaler Before supplying the CPU and the peripherals, the main clock is divided by a factor 2 to30 to reduce the

25A/T8xC51214164G–SCR–07/06Table 9. CKCON0 RegisterCKCON0 - Clock Control Register (8Fh)Reset Value = X0X0 X000b76543210-WDX2- SIX2 - T1X2T0X2X2Bit N

26 A/T8xC51214164G–SCR–07/06Table 10. CKCON1 RegisterCKCON1 - Clock Control Register (AFh)Reset Value = XXXX 0XXXb76543210----SCX2---Bit NumberBit

27A/T8xC51214164G–SCR–07/06DC/DC Clock The DC/DC block needs a clock with a 50% duty cycle. The frequency must also respecta value between 3.68 MHz an

28 A/T8xC51214164G–SCR–07/06

29A/T8xC51214164G–SCR–07/06Smart Card Interface Block (SCIB)Introduction The SCIB provides all signals to directly interface a smart card. Compliance

3A/T8xC51214164G–SCR–07/06Pin Description Figure 2. 24-pin SSOP PinoutFigure 3. QFN32 PinoutP1.1/CC8 P1.4/CCLKP1.0/CIORSTP1.5/CRST 1 P1.3/CC4P1.2/C

30 A/T8xC51214164G–SCR–07/06Block Diagram The Smart Card Interface Block diagram is shown in Figure 14. Figure 14. SCIB Block DiagramFunctional Desc

31A/T8xC51214164G–SCR–07/06the different counters. One of the most important counters is the guard time counter thatgives time slots corresponding to

32 A/T8xC51214164G–SCR–07/06Waiting Time Counter (WT) The WT counter is a 24 bits down counter which can be loaded with the value containedin the SCW

33A/T8xC51214164G–SCR–07/06Figure 17. T = 0 ModeFigure 18. T = 1 Mode Power-on and Power-off FSM In this state, the machine applies the signals on

34 A/T8xC51214164G–SCR–07/06Interrupt Generator There are several sources of interruption but the SCIB macro-cell issues only one inter-rupt signal:

35A/T8xC51214164G–SCR–07/06Other FeaturesClock The Ck-ISO input must be in the range 1 - 5 MHz according to ISO7816.The ISO Clock diagram and the conf

36 A/T8xC51214164G–SCR–07/06Figure 22. Alternate CardCard Presence Input The internal pull-up on Card Presence input can be disconnected in order to

37A/T8xC51214164G–SCR–07/06DC/DC Converter The Smart Card supply voltage (CVCC) is generated by the integrated DC/DC converter.It is controlled by sev

38 A/T8xC51214164G–SCR–07/06Registers Description Table 15. SCICR RegisterSCICR (S:B6h, SCRS = 1) Smart Card Interface Control RegisterReset Value =

39A/T8xC51214164G–SCR–07/06Table 16. SCCON RegisterSCCON (S:ACh, SCRS = 0) Smart Card Contacts RegisterReset Value = 0X00 0000b76543210CLK - CARDC8 C

4 A/T8xC51214164G–SCR–07/06Figure 4. PLCC52 Pinout 21 22 26252423 292827 30 31 5 4 3 2 1 6 52 51 50 49 48LICVCCVSSDVCCP0.1/AD1P0.0/AD0P0.2/AD2P

40 A/T8xC51214164G–SCR–07/06Table 17. SCISR RegisterSCISR (S:ADh, SCRS = 0) Smart Card UART Interface Status RegisterReset Value = 1000 0000b7654321

41A/T8xC51214164G–SCR–07/06Table 18. SCIIR RegisterSCIIR (S:AEh, SCRS = 0) Smart Card UART Interrupt Identification Register (read only)Reset Value =

42 A/T8xC51214164G–SCR–07/06Table 19. SCIER RegisterSCIER (S:AEh, SCRS = 1) Smart Card UART Interrupt Enable RegisterReset Value = 0X00 0000b765 4 3

43A/T8xC51214164G–SCR–07/06Table 20. SCSR RegisterSCSR (S:ABh) Smart Card Selection RegisterReset Value = XXX0 1000bTable 21. SCTBUF RegisterSCTBUF

44 A/T8xC51214164G–SCR–07/06Table 22. SCRBUF RegisterSCRBUF (S:AA read-only, SCRS = 1) Smart Card Receive Buffer RegisterReset Value = 0000 0000bTab

45A/T8xC51214164G–SCR–07/06Table 24. SCETU0 RegisterSCETU0 (S:ACh, SCRS = 1) Smart Card ETU Register 0Reset Value = 0111 0100bTable 25. SCGT1 Regist

46 A/T8xC51214164G–SCR–07/06Table 27. SCWT2 RegisterSCWT2 (S:B6h, SCRS = 0) Smart Card Character/Block Wait Time Register 2Reset Value = 0000 0000bT

47A/T8xC51214164G–SCR–07/06Interrupt System The T8xC5121 has a total of 6 interrupt vectors: four external interrupts (INT0, INT1/OE,CPRES, RxD), two

48 A/T8xC51214164G–SCR–07/06A low-priority interrupt can be interrupted by a high priority interrupt, but not by anotherlow-priority interrupt. A hig

49A/T8xC51214164G–SCR–07/06Table 32. IE0 RegisterReset Value = 0XX0 0000bBit addressable76543210EA - - ES ET1 EX1 ET0 EX0Bit NumberBit Mnemoni

5A/T8xC51214164G–SCR–07/06Signals All the T8xC5121 signals are detailed in Table 1.The port structure is described in Section “Port Structure Descript

50 A/T8xC51214164G–SCR–07/06Table 33. IE1 RegisterReset Value = XXXX 0XXXb76543210----ESCI---Bit NumberBit Mnemonic Description7-ReservedThe

51A/T8xC51214164G–SCR–07/06Table 34. TCON RegisterTCON (S:88h)Timer 0/Counter Control RegisterReset Value = 0000 0000b76543210TF1 TR1 TF0 TR0 IE1 IT1

52 A/T8xC51214164G–SCR–07/06Table 35. ISEL RegisterReset Value = 0000 0100b76543210CPLEV OEIT PRESIT RXIT OELEV OEEN PRESEN RXEN Bit NumberBit

53A/T8xC51214164G–SCR–07/06Table 36. IPL0 RegisterReset Value = XXX0 0000bBit addressable76543210- - - PSL PT1L PX1L PT0L PX0LBit NumberBit Mn

54 A/T8xC51214164G–SCR–07/06Table 37. IPL1 RegisterReset Value = XXXX 0XXXbBit addressable76543210----PSCIL---Bit NumberBit Mnemonic Descript

55A/T8xC51214164G–SCR–07/06Table 38. IPH0 RegisterReset Value = XXX0 0000b76543210- - - PSH PT1H PX1H PT0H PX0HBit NumberBit Mnemonic Descript

56 A/T8xC51214164G–SCR–07/06Table 39. IPH1 RegisterReset Value = XXXX 0XXXb76543210----PSCIH---Bit NumberBit Mnemonic Description7-ReservedTh

57A/T8xC51214164G–SCR–07/06LED Ports ConfigurationThe current source of the LED Ports can be adjusted to 3 different values: 2, 4 or 10 mA.The LED out

58 A/T8xC51214164G–SCR–07/06Dual Data Pointer T8xC5121 contains a Dual Data Pointer accelerating data memory block moves. TheStandard 80C52 Data Poin

59A/T8xC51214164G–SCR–07/06Table 43. AUXR1 RegisterAUXR1 - Dual Pointer Selection Register (A2h)Reset value = XXXX XXX0b76543210-------DPSBit NumberB

6 A/T8xC51214164G–SCR–07/06P3.0 RxD EVCCIUART functionReceive data inputI/OInput/Output functionP3.0 is a bi-directional I/O port with internal pull-

60 A/T8xC51214164G–SCR–07/06Memory ManagementProgram Memory All the T8xC5121 versions implement 16 Kbytes of ROM memory, 256 Bytes RAM and256 Bytes

61A/T8xC51214164G–SCR–07/06Memory Mapping In the products versions, the following internal spaces are defined:•RAM•XRAM• CRAM: 16 KBytes Program RAM M

62 A/T8xC51214164G–SCR–07/06If a serial communication device (as described above: TWI or RS232) is detected, theprogram download its content in the i

63A/T8xC51214164G–SCR–07/06Figure 25. CRAM and ROM MappingsT83C5121 with Mask ROM VersionIn this version, the customer program is masked in 16 Kbytes

64 A/T8xC51214164G–SCR–07/06Figure 26. Hardware in Relation with the Two Communication ProtocolsEEPROM Mapping The 16K Bytes EEPROM mapping is the f

65A/T8xC51214164G–SCR–07/06Bootloader Functional DiagramAs described in Section “ROM Configuration Byte”, page 60a ROM bit BLJRB (BootLoader Jump ROM

66 A/T8xC51214164G–SCR–07/06In-System Programming TimingsThe download from the internal EEPROM to CRAM is executed after 4 seconds whenoperating at 1

67A/T8xC51214164G–SCR–07/06***************************************************************************************************Table 47. Synthesis of

68 A/T8xC51214164G–SCR–07/06The only mean to remove the security level 2 is to send a Full Chip Erase command.Table 48. Synthesis of Security Mechan

69A/T8xC51214164G–SCR–07/06Table 49. Valid Software Security Byte ValuesUART ProtocolOverview The serial protocol used is described below. Physical L

7A/T8xC51214164G–SCR–07/06I/OInput/Output functionP3.4 is a bi-directional I/O port with internal pull-ups.ITimer 0 function: External clock inputWhen

70 A/T8xC51214164G–SCR–07/06• Record Type:– Record Type specifies the command type. This field is used to interpret the remaining information within

71A/T8xC51214164G–SCR–07/06Autobaud The ISP feature allows a wide range of baud rates in the user application. It is alsoadaptable to a wide range of

72 A/T8xC51214164G–SCR–07/06UART ISP Intern. EEP Programming SSB level 1 must be set (done, if selected, at ISP Programming or Ext EEP Donwload)UART

73A/T8xC51214164G–SCR–07/06Timers/CountersIntroduction The T8xC5121 implements two general-purpose, 16-bit Timer 0s/Counters. Althoughthey are identif

74 A/T8xC51214164G–SCR–07/06Timer 0 Timer 0 functions as either a Timer 0 or an event Counter in four operating modes.Figure 28 through Figure 31 sho

75A/T8xC51214164G–SCR–07/06Figure 29. Timer 0/Counter x (x = 0 or 1) in Mode 1Mode 2 (8-bit Timer 0 with Auto-Reload)Mode 2 configures Timer 0 as an

76 A/T8xC51214164G–SCR–07/06Figure 31. Timer 0/Counter 0 in Mode 3: Two 8-bit CountersTR0TCON.4TF0TCON.5INT001GATE0TMOD.3OverflowTimer 0InterruptReq

77A/T8xC51214164G–SCR–07/06Timer 1 Timer 1 is identical to Timer 0 except for Mode 3 which is a hold-count mode. The fol-lowing comments help to under

78 A/T8xC51214164G–SCR–07/06Registers Table 55. TCON RegisterTCON (S:88h) - Timer 0/Counter Control RegisterReset Value = 0000 0000b76543210TF1 TR1

79A/T8xC51214164G–SCR–07/06Reset Value = 0000 0000bTable 56. TMOD RegisterTMOD (S:89h) - Timer 0/Counter Mode Control Registers76543210GATE1 C/T1# M1

8 A/T8xC51214164G–SCR–07/06RST VCCI/O Reset inputHolding this pin low for 64 oscillator periods while the oscillatoris running resets the device. The

80 A/T8xC51214164G–SCR–07/06Table 57. TH0 RegisterTH0 (S:8Ch) - Timer 0 High Byte Register.Reset Value = 0000 0000bTable 58. TL0 RegisterTL0 (S:8Ah

81A/T8xC51214164G–SCR–07/06Serial I/O Port The serial I/O port is entirely compatible with the serial I/O port in the 80C52. It provides both synchron

82 A/T8xC51214164G–SCR–07/06Figure 34. UART Timings in Mode 1Figure 35. UART Timings in Modes 2 and 3Automatic Address RecognitionThe automatic add

83A/T8xC51214164G–SCR–07/06To address a device by its individual address, the SADEN mask byte must be 11111111b.For example:SADDR0101 0110bSADEN1111 1

84 A/T8xC51214164G–SCR–07/06Reset Addresses On reset, the SADDR, SADEN register are initialized to 00h, i.e. the given and broad-cast addresses are X

85A/T8xC51214164G–SCR–07/06UART Control Registers Table 61. SADEN RegisterSADENSlave Address Mask Register (B9h)Reset Value = 0000 0000bTable 62. SA

86 A/T8xC51214164G–SCR–07/06UART Timings The following description will be included in L version:Mode Selection SM0 and SM1 bits in SCON register (se

87A/T8xC51214164G–SCR–07/06Figure 37. Internal Baud Rate Generator Block DiagramSynchronous Mode (Mode 0) Mode 0 is a half-duplex, synchronous mode,

88 A/T8xC51214164G–SCR–07/06Reception (Mode 0) To start a reception in mode 0, write to SCON register clearing SM0, SM1 and RI bitsand setting the RE

89A/T8xC51214164G–SCR–07/06Asynchronous Modes (Modes 1, 2 and 3)The Serial Port has one 8-bit and two 9-bit asynchronous modes of operation. Figure 43

9A/T8xC51214164G–SCR–07/06ONLY FOR PLCC52 version P0[7:0] AD[7:0] VCCI/O Input/Output function Port 0P0 is an 8-bit open-drain bi-directional I/O port

90 A/T8xC51214164G–SCR–07/06Framing Error Detection (Modes 1, 2 and 3)Framing error detection is provided for the three asynchronous modes. To enable

91A/T8xC51214164G–SCR–07/06Table 65. Internal Baud Rate Generator ValueNotes: 1. These frequencies are achieved in X1 mode, FPER = FOSC ÷ 2.2. These

92 A/T8xC51214164G–SCR–07/06Table 66. BRL (S:91h)BRL RegisterBaud Rate Generator Reload RegisterReset Value = 0000 0000b76543210BRL7 BRL6 BRL5 BRL4

93A/T8xC51214164G–SCR–07/06Reset Value = XXX0 0000bTable 67. SCON RegisterSCON (S:98h)Serial Control Registe76543210FE/SM0 SM1 SM2 REN TB8 RB8 TI RIB

94 A/T8xC51214164G–SCR–07/06Table 68. BDRCON Register BDRCONBaud Rate Control Register (9Bh)Reset Value = XXX0 0000b76543210- - - BRR TBCK RBCK SPD

95A/T8xC51214164G–SCR–07/06Table 69. SIOCON RegisterSerial Input Output Configuration RegisterRegister (91h)Reset Value = 00XX 0000b76543210PMSOEN1 P

96A/T8xC51214132C–SCR–07/06Hardware Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be sub-jected to software u

97A/T8xC51214132C–SCR–07/06Table 71. WDTPRG RegisterWDTPRG - Watchdog Timer Out Register (0A7h)Reset Value = XXXX X000WDT during Power-down and IdleI

98 A/T8xC51214164G–SCR–07/06Electrical CharacteristicsAbsolute Maximum Ratings DC Parameters TA = -40°C to +85°C; VSS = 0 V; VCC = 2.85V to 5.4V; F =

99A/T8xC51214164G–SCR–07/06The operating conditions for ICC Tests are the following:Figure 51. ICC Test Condition, Active ModeFigure 52. ICC Test Co