Rainbow-electronics AT45DB011B Bedienungsanleitung

11-megabit2.7-volt Only DataFlash®AT45DB011BFeatures• Single 2.7V - 3.6V Supply• Serial Peripheral Interface (SPI) Compatible• 20 MHz Max Clock Freque

10AT45DB011B1984E–DFLSH–10/02RESET: A low state on the reset pin (RESET) will terminate the operation in progress andreset the internal state machine

11AT45DB011B1984E–DFLSH–10/02Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock

AT45DB011B12Note: r = Reserved BitP = Page Address BitB = Byte/Buffer Address Bitx = Don’t CareTable 4. Detailed Bit-level Addressing SequenceOpcode

13AT45DB011B1984E–DFLSH–10/02Note: 1. Icc1 during a buffer read is 20mA maximum.DC CharacteristicsSymbol Parameter Condition Min Typ Max UnitsISBStand

14AT45DB011B1984E–DFLSH–10/02Input Test Waveforms and Measurement LevelstR, tF < 3 ns (10% to 90%)Output Test LoadAC WaveformsTwo different timing

15AT45DB011B1984E–DFLSH–10/02Reset Timing (Inactive Clock Polarity Low Shown)Note: The CS signal should be in the high state before the RESET signal i

16AT45DB011B1984E–DFLSH–10/02Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.Main Memory Pa

17AT45DB011B1984E–DFLSH–10/02Read OperationsThe following block diagram and waveforms illustrate the various read sequences available.Main Memory Page

18AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity LowContinuous Array Read (Opcode: 68H)Main Memory Page Read (Opc

19AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)Buffer Read (Opcode: 54H)Status Register Read (Op

2AT45DB011B1984E–DFLSH–10/02layout, increases system reliability, minimizes switching noise, and reduces package size andactive pin count. The device

20AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity HighContinuous Array Read (Opcode: 68H)Main Memory Page Read (Op

21AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)Buffer Read (Opcode: 54H)Status Register Read (O

22AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 0Continuous Array Read (Opcode: E8H)Main Memory Page Read (Opcode: D2H)SI11XXXC

23AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 0 (Continued)Buffer Read (Opcode: D4H)Status Register Read (Opcode: D7H)SI11010

24AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 3Continuous Array Read (Opcode: E8H)Main Memory Page Read (Opcode: D2H)SI11XXXC

25AT45DB011B1984E–DFLSH–10/02Detailed Bit-level Read Timing – SPI Mode 3 (Continued)Buffer Read (Opcode: D4H)Status Register Read (Opcode: D7H)SI11010

26AT45DB011B1984E–DFLSH–10/02Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire ArrayNotes: 1. This type of algorithm is us

27AT45DB011B1984E–DFLSH–10/02Figure 2. Algorithm for Randomly Modifying DataNotes: 1. To preserve data integrity, each page of a DataFlash sector mus

28AT45DB011B1984E–DFLSH–10/02Ordering InformationfSCK (MHz)ICC (mA)Ordering Code Package Operation RangeActive Standby20 10 0.01 AT45DB011B-CCAT45DB01

29AT45DB011B1984E–DFLSH–10/02Packaging Information9C1 – CBGA 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 9C1, 9-ball (3 x 3 Array

3AT45DB011B1984E–DFLSH–10/02Memory Architecture DiagramDevice OperationThe device operation is controlled by instructions from the host processor. The

30AT45DB011B1984E–DFLSH–10/028S2 – EIAJ SOIC2325 Orchard ParkwaySan Jose, CA 95131TITLEDRAWING NO.RREV. 8S2, 8-lead, 0.209" Body, Plastic Small

31AT45DB011B1984E–DFLSH–10/0214X – TSSOP 2325 Orchard Parkway San Jose, CA 95131TITLEDRAWING NO.RREV. 14X (Formerly "14T"), 14-lead (4.4

Printed on recycled paper.© Atmel Corporation 2002.Atmel Corporation makes no warranty for the use of its products, other than those expressly contai

4AT45DB011B1984E–DFLSH–10/02CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memoryarray, the Continuous Array Read comman

5AT45DB011B1984E–DFLSH–10/02STATUS REGISTER READ: The status register can be used to determine the device’sready/busy status, the result of a Main Mem

6AT45DB011B1984E–DFLSH–10/02BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previouslyerased page within main memory can be programmed wi

7AT45DB011B1984E–DFLSH–10/02MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combination ofthe Buffer Write and Buffer to Main Memory Page

8AT45DB011B1984E–DFLSH–10/02Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before a

9AT45DB011B1984E–DFLSH–10/02Operation Mode SummaryThe modes described can be separated into two groups – modes which make use of the Flashmemory array