Rainbow-electronics AT45DB642 Bedienungsanleitung

8784B–DFLASH–11/2012Features Single 2.3V - 3.6V or 2.5V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Sup

10AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20126. Program and Erase Commands6.1 Buffer WriteUtilizing the Buffer Write command allows data c

11AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012When a low-to-high transition occurs on the CS pin, the device will program the data stored i

12AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012buffer is reached, then the device will wrap around back to the beginning of the buffer. When

13AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 6-1. Block Erase Addressing6.8 Sector EraseThe Sector Erase command can be used to indi

14AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 6-2. Sector Erase Addressing6.9 Chip EraseThe Chip Erase command allows the entire main

15AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20126.10 Program/Erase Suspend(1)In some code and data storage applications, it may not be possib

16AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 6-4. Operations Allowed and Not Allowed During SuspendCommandOperation During Program S

17AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20126.11 Program/Erase Resume(1)The Program/Erase Resume command allows a suspended program or er

18AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20127. Sector ProtectionTwo protection methods, hardware and software controlled, are provided fo

19AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 7-2. Disable Sector Protection 7.2 Hardware Controlled ProtectionSectors specified for

2AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012DescriptionThe Adesto® AT45DB321E is a 2.3V or 2.5V minimum, serial-interface sequential acces

20AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20127.3 Sector Protection RegisterThe nonvolatile Sector Protection Register specifies which sect

21AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 7-4. Erase Sector Protection Register 7.3.2 Program Sector Protection Register Once th

22AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20127.3.3 Read Sector Protection RegisterTo read the Sector Protection Register, an opcode of 32h

23AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20128. Security Features8.1 Sector LockdownThe device incorporates a sector lockdown mechanism th

24AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 8-3. Sector 0 (0a and 0b) Sector Lockdown Register Byte ValueTable 8-4. Read Sector Loc

25AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20128.2 Security RegisterThe device contains a specialized Security Register that can be used for

26AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20128.2.2 Reading the Security RegisterTo read the Security Register, an opcode of 77h and three

27AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20129. Additional Commands9.1 Main Memory Page to Buffer TransferA page of data can be transferre

28AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012program the data from the buffer back into same page of main memory. The operation is interna

29AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 9-2. Status Register Format – Byte 2Note: 1. R = Readable only9.4.1 RDY/BUSY BitThe RDY

3AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 1-1. Pin ConfigurationsSymbol Name and FunctionAsserted StateTypeCSChip Select: Assertin

30AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20129.4.6 EPE Bit The EPE bit indicates whether the last erase or program operation completed suc

31AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201210. Deep Power-DownDuring normal operation, the device will be placed in the standby mode to

32AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201210.1 Resume from Deep Power-DownIn order to exit the Deep Power-Down mode and resume normal d

33AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201210.2 Ultra-Deep Power-DownThe Ultra-Deep Power-Down mode allows the device to consume far les

34AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201210.2.1 Exit Ultra-Deep Power-DownTo exit from the Ultra-Deep Power-Down mode, the CS pin must

35AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201211. Buffer and Page Size ConfigurationThe memory array of DataFlash devices is actually large

36AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201212. Manufacturer and Device ID ReadIdentification information can be read from the device to

37AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 12-1. Read Manufacturer and Device IDTable 12-3. EDI DataByte Number Bit 7 Bit 6 Bit 5

38AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201213. Software ResetIn some applications, it may be necessary to prematurely terminate a progra

39AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201214. Operation Mode SummaryThe commands described previously can be grouped into four differen

4AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20122. Block DiagramFigure 2-1. Block DiagramFlash Memory ArrayI/O InterfaceSCKCSRESETVCCGNDWPSOSI

40AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201215. Command TablesTable 15-1. Read CommandsTable 15-2. Program and Erase CommandsCommand Opco

41AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 15-3. Protection and Security CommandsTable 15-4. Additional CommandsTable 15-5. Legacy

42AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 15-6. Detailed Bit-level Addressing Sequence for Binary Page Size (512 bytes)Note: X =

43AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Table 15-7. Detailed Bit-level Addressing Sequence for Standard DataFlash Page Size (528 byte

44AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201216. Power-On/Reset StateWhen power is first applied to the device, or when recovering from a

45AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201217. System ConsiderationsThe serial interface is controlled by the Serial Clock (SCK), Serial

46AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201218. Electrical Specifications18.1 Absolute Maximum Ratings*18.2 DC and AC Operating RangeTemp

47AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201218.3 DC Characteristics Notes: 1. Typical values measured at 3.0V at 25C.2. ICC2 during a Bu

48AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201218.4 AC CharacteristicsNote: 1. Values are based on device characterization, not 100% tested

49AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201218.5 Program and Erase CharacteristicsNotes: 1. Values are based on device characterization,

5AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20123. Memory ArrayTo provide optimal flexibility, the AT45DB321E memory array is divided into thr

50AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201221. Utilizing the RapidS FunctionTo take advantage of the RapidS function's ability to o

51AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 21-2. Command Sequence for Read/Write Operations for Page Size 512 bytes (Except Statu

52AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201222. AC WaveformsFour different timing waveforms are shown in Figure 22-1 through Figure 22-4.

53AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 22-3. Waveform 3 = RapidS Mode 0Figure 22-4. Waveform 4 = RapidS Mode 3CSSCKSISOtCSSVa

54AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201223. Write OperationsThe following block diagram and waveforms illustrate the various write se

55AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201224. Read OperationsThe following block diagram and waveforms illustrate the various read sequ

56AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 24-3. Main Memory Page to Buffer TransferData From the selected Flash Page is read int

57AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201225. Detailed Bit-level Read Waveforms: RapidS Mode 0/Mode 3Figure 25-1. Continuous Array Read

58AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 25-4. Main Memory Page Read (Opcode D2h)Figure 25-5. Buffer Read (Opcode D4h or D6h)Fi

59AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 25-7. Read Sector Protection Register (Opcode 32h)Figure 25-8. Read Sector Lockdown Re

6AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20124. Device OperationThe device operation is controlled by instructions from the host processor.

60AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 25-10. Status Register Read (Opcode D7h)Figure 25-11. Manufacturer and Device Read (Op

61AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201226. Auto Page Rewrite FlowchartFigure 26-1. Algorithm for Programming or Re-programming of th

62AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012Figure 26-2. Algorithm for Programming or Re-programming of the Entire Array RandomlyNotes: 1

63AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201227. Ordering Information27.1 Ordering DetailDevice GradeH = Green, NiPdAu lead finish, I

64AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201227.2 Ordering Codes (Standard DataFlash Page Size)Notes: 1. The shipping carrier suffix is no

65AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201227.3 Ordering Codes (Binary Page Size)Notes: 1. The shipping carrier suffix is not marked on

66AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201228. Packaging Information28.1 8S2 – 8-lead EIAJ SOICTITLEDRAWING NO. GPCREV.Package Drawin

67AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201228.2 8MA1 – 8-pad UDFNTITLEDRAWING NO.GPCREV.Package Drawing Contact:[email protected]

68AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201228.3 9CC1 — 9-ball UBGADRAWING NO. REV. GPCTITLEPackage Drawing Contact:[email protected]

69AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201229. Revision HistoryDoc. Rev. Date Comments8784B 11/2012Add Legacy Commnads table.Update to A

7AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/20125. Read CommandsBy specifying the appropriate opcode, data can be read from the main memory or

70AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/201230. Errata30.1 Program and Erase CommandsIssue: The AT45DB321E incorporates a new Program Era

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8AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012A low-to-high transition on the CS pin will terminate the read operation and tri-state the out

9AT45DB321E [PRELIMINARY DATASHEET]8784B–DFLASH–11/2012of the main memory array to read and the last 10 bits (BA9 - BA0) of the 23-bit address sequen