1 of 14 110602 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions
DS1371 10 of 14 Special Purpose Registers The DS1371 has two additional registers (07h–08h) that control the WD/ALM counter, square-wave output, and
DS1371 11 of 14 Status Register (08h) Bit # 7 6 5 4 3 2 1 0 Name OSF 0 0 0 0 0 0 AF Default 1 0 0 0 0 0 0 — Bit 7/Oscillator Stop Flag (OSF). A
DS1371 12 of 14 Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration
DS1371 13 of 14 Figures 6 and 7 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of dat
DS1371 14 of 14 Figure 6. 2-Wire Write Protocol Figure 7. 2-Wire Read Protocol Chip Information TRANSISTOR COUNT: 11,036 SUBSTRATE CO
DS1371 2 of 14 ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Pin Relative to Ground -0.3V to +6.0VVoltage Range on SDA, SCL, and WDS Relative to Gr
DS1371 3 of 14 AC ELECTRICAL CHARACTERISTICS (VCC = 1.7V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 8) PARAMETER SYMBOL CONDITIONS
OSCILLATOR FREQUENCY vs. VCCDS1371 toc06VCC (V)FREQUENCY (Hz)5.34.84.33.83.32.82.31.832767.6132767.6632767.7132767.763.767.561.3IOSC0 vs. WDS FREQUENC
DS1371 5 of 14 Figure 1. Timing Diagram Figure 2. Functional Diagram
DS1371 6 of 14 PIN DESCRIPTION PIN NAME FUNCTION 1, 2 X1, X2 These signals are connections for a standard 32.768kHz quartz crystal. The internal o
DS1371 7 of 14 Table 1. Crystal Specifications* PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency FO 32.768 kHz Series Resistance ESR 45
DS1371 8 of 14 Address Map Table 2 shows the address map for the registers of the DS1371. During a multibyte access, when the address pointer reaches
DS1371 9 of 14 Time-of-Day Counter The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the address range
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