Rainbow-electronics DS1868 Bedienungsanleitung

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1 of 14 100899
FEATURES
Ultra-lowpower consumption, quiet, pumpless
design
Two digitally controlled, 256-position
potentiometers
Serial port provides means for setting and
reading both potentiometers
Resistors can be connected in series to
provide increased total resistance
20-pin TSSOP, 16-pin SOIC, and 14-pin DIP
packages are available.
Resistive elements are temperature
compensated to ±0.3 LSB relative linearity
Standard resistance values:
- DS1868-10 10 k
- DS1868-50 50 k
- DS1868-100 100 k
+5V or ±3V operation
Operating Temperature Range:
- Industrial: -40°C to 85°C
PIN ASSIGNMENT
PIN DESCRIPTION
L0, L1 - Low End of Resistor
H0, H1 - High End of Resistor
W0, W1 - Wiper Terminal of Resistor
S
OUT
- Stacked Configuration Output
RST - Serial Port Reset Input
DQ - Serial Port Data Input
CLK - Serial Port Clock Input
C
OUT
- Cascade Port Output
V
CC
- +5 Volt Supply
GND - Ground Connections
NC - No Internal Connection
V
B
- Substrate Bias Voltage
DNC - Do Not Connect
*All GND pins must be connected to ground.
DESCRIPTION
The DS1868 Dual Digital Potentiometer Chip consists of two digitally controlled solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
DS1868
Dual Digital Potentiometer Chip
www.dalsemi.com
20-Pin TSSOP (173-mil)
V
B
DNC
H1
L1
W1
RST
CLK
DNC
DNC
GND
V
CC
DNC
DNC
S
OUT
W0
H0
L0
C
OUT
DNC
DQ
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DS1868S 16-Pin SOIC (300-mil)
V
B
NC
H1
L1
W1
RST
CLK
GND
V
CC
NC
S
OUT
W0
H0
L0
C
OUT
DQ
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
14-Pin DIP (300-mil)
V
B
H1
L1
W1
RST
CLK
V
CC
S
OUT
W0
H0
L0
C
OUT
14
13
12
11
10
8
1
2
3
4
5
7
DQ
GND
9
6
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Inhaltsverzeichnis

Seite 1 - DESCRIPTION

1 of 14 100899FEATURES Ultra-lowpower consumption, quiet, pumplessdesign Two digitally controlled, 256-positionpotentiometers Serial port provides

Seite 2 - OPERATION

DS186810 of 14

Seite 3 - STACKED CONFIGURATION

DS186811 of 14CAPACITANCE (tA=25°C)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESInput Capacitance CIN5 pF 3, 6Output Capacitance COUT7 pF 3, 6AC ELECTRICAL

Seite 4 - , will be that of the

DS186812 of 14TIMING DIAGRAMS Figure 9(a) 3-Wire Serial Interface General Overview(b) Start of Communication Transaction(c) End of Communication Trans

Seite 5 - CASCADE OPERATION

DS186813 of 14DIGITAL OUTPUT LOAD SCHEMATIC Figure 10TYPICAL SUPPLY CURRENT VS. SERIAL CLOCK RATE Figure 11

Seite 6

DS186814 of 14DS1868 20-PIN TSSOPDIM MIN MAXA MM-1.10A1 MM0.05 -A2 MM0.75 1.05C MM0.09 0.18L MM0.50 0.70e1 MM0.65 BSCB MM0.18 0.30D MM6.40 6.90E MM4.4

Seite 7

DS18682 of 14wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiperoutput. Communication and co

Seite 8

DS18683 of 14DS1868 BLOCK DIAGRAM Figure 1I/O SHIFT REGISTER Figure 2Transmission of data always begins with the stack select bit followed by the pote

Seite 9

DS18684 of 14potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S OUT, will be that of thepotentiometer-1 wiper.

Seite 10 - 10 of 14

DS18685 of 14STACKED CONFIGURATION Figure 3CASCADE OPERATIONA feature of the DS1868 is the ability to control multiple devices from a single processor

Seite 11 - =5.0V ± 10%)

DS18686 of 14ABSOLUTE AND RELATIVE LINEARITYAbsolute linearity is defined as the difference between the actual measured output voltage and theexpected

Seite 12 - TIMING DIAGRAMS Figure 9

DS18687 of 14DS1868 ABSOLUTE AND RELATIVE LINEARITY Figure 6TYPICAL APPLICATION CONFIGURATIONSFigures 7 and 8 show two typical application configurati

Seite 13 - 13 of 14

DS18688 of 14VARIABLE GAIN AMPLIFIER Figure 7FIXED GAIN ATTENUATOR Figure 8

Seite 14 - DS1868 20-PIN TSSOP

DS18689 of 14ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground (VB=GND) -1.0V to +7.0VVoltage on Any Pin when VB=-3.3V -3.3V to +4.7VOper

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