
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
______________________________________________________________________________________ 11
MAX9217
PAR-TO-SER
TIMING AND
CONTROL
PLL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
V
CC
130Ω
IN
OUT
82Ω 82Ω
CMF
MOD0
RNG1
RNG0
MOD1
MAX9218
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
R/F
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
*CAPS CAN BE AT EITHER END.
*
*
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
MAX9217
PAR-TO-SER
TIMING AND
CONTROL
PLL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
130Ω
V
CC
130Ω
IN
OUT
82Ω 82Ω
CMF
MOD0
RNG1
RNG0
MOD1
MAX9218
SER-TO-PAR
TIMING AND
CONTROL
PLL
DC BALANCE/
DECODE
1
0
R/F
OUTEN
RGB_OUT
LOCK
PWRDWN
REF_IN
PCLK_OUT
DE_OUT
CNTL_OUT
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
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