Rainbow-electronics ATR0601 Bedienungsanleitung

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Features
Very Low Power Design (40 mW)
Single IF Architecture
Excellent Noise Performance
1.5-bit ADC On Chip
Small QFN Package (4 mm × 4 mm, 24 pins)
Highly integrated, Few External Components
Advanced BiCMOS Technology (UHF6s)
Non ESD Sensitive Device
1. Description
The ATR0601 is a single IF GPS front-end IC, designed to meet the requirements of
mobile and automotive applications. Excellent RF performance combined with low
noise figure enables high quality GPS solutions and it's very low power consumption
fits perfectly to portable devices. Featuring a balanced XTO and a fully integrated bal-
anced frequency synthesizer, only few external components are required. The
ATR0601 offers a complete autonomous mode, utilizing the on chip AGC in closed
loop operation, to set the gain of the IF VGA. Alternatively, in combination with the
baseband processor ATR0621 the optimum gain of the IF VGA can be computed and
set by software, using the digital SDI interface.
Figure 1-1. Block Diagram
XTO
PMSS
Logic
D
A
VCO
PLL
D
A
BPI
T
EST
MO
GND
NBPI
BP
NBP
VCC
VCC
VDIG
PUXTO
PURF
RF
NRF
XTO
NXTO
X
NX
SDI
SL
SH
SC
AGCO
EGC
1
GPS Front-end
IC
ATR0601
Preliminary
Rev. 4866A–GPS–08/05
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Inhaltsverzeichnis

Seite 1 - Preliminary

Features•Very Low Power Design (40 mW)•Single IF Architecture•Excellent Noise Performance •1.5-bit ADC On Chip•Small QFN Package (4 mm × 4 mm, 24 pin

Seite 2

104866A–GPS–08/05ATR0601 [Preliminary] Figure 9-3. Equivalent Application Examples Using a GPS TCXO (Please see Table 9-3 on page 12) Figure 9-4. Ap

Seite 3

114866A–GPS–08/05 ATR0601 [Preliminary] Figure 9-5. Recommended IF-filter: Layout versus Schematic Note: Mutual inductance between the four inductors

Seite 4

124866A–GPS–08/05ATR0601 [Preliminary] Table 9-3. Specification of GPS TCXOs Appropriate for the Application Example Shown in Figure 9-3 on page 10P

Seite 5

134866A–GPS–08/05 ATR0601 [Preliminary] 10. Demonstration BoardFigure 10-1. Schematic of Demonstration Board 20PUXTOJ9J81561212312323AGCO EGC21121212

Seite 6

144866A–GPS–08/05ATR0601 [Preliminary] Figure 10-2. Illustration of Demonstration Board Table 10-1. BOM of Demonstration BoardQty Value Device Parts

Seite 7

154866A–GPS–08/05 ATR0601 [Preliminary] 11. Recommended FootprintFigure 11-1. Recommended Footprint (QFN24 - 4 mm × 4 mm)

Seite 8

164866A–GPS–08/05ATR0601 [Preliminary] 13. Package Information 12. Ordering InformationExtended Type Number Package RemarksATR0601-PFQW QFN24, 4 ×

Seite 9

Printed on recycled paper.4866A–GPS–08/05© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® an

Seite 10 - ATR0601 [Preliminary]

24866A–GPS–08/05ATR0601 [Preliminary] 2. Pin ConfigurationFigure 2-1. Pinning QFN24 123456181716151413789101112242322212019Paddle GNDVDIGAGCONXTONXX

Seite 11 - ATR0601 [Preliminary]

34866A–GPS–08/05 ATR0601 [Preliminary] 3. Functional Description3.1 General DescriptionThe ATR0601 GPS receiver IC has been especially designed for G

Seite 12

44866A–GPS–08/05ATR0601 [Preliminary] 3.7 VGA/AGCThe output of the IF-Filter drives an on-chip Variable Gain Amplifier (VGA) which is combined with

Seite 13

54866A–GPS–08/05 ATR0601 [Preliminary] 4. Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent d

Seite 14

64866A–GPS–08/05ATR0601 [Preliminary] 2Mixer2.1 Output frequency fXTO = 23.104 MHz 13, 14 fIF96.764 MHz A2.2Input impedance (balanced)fRF = 1575.42

Seite 15

74866A–GPS–08/05 ATR0601 [Preliminary] 8. TimingFigure 8-1. Recommended Power-up/down Sequence Figure 8-2. Recommended Sleep-mode Sequence Figure 8-3

Seite 16

84866A–GPS–08/05ATR0601 [Preliminary] Figure 8-5. Synchronous Shut-down Behaviour of SC with Respect to PUxto Figure 8-6. Data Outputs SL and SH are

Seite 17 - Regional Headquarters

94866A–GPS–08/05 ATR0601 [Preliminary] 9. Application CircuitFigure 9-1. Application Example Using a GPS Crystal with ESRtyp = 12Ω (Please see Table

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