Rainbow-electronics ADC08D1000 Bedienungsanleitung PDF herunterladen (Seite 10)

Converter Electrical Characteristics (Continued)

[Note: This product is currently in development. As such, the parameters specified in this section are DESIGN TAR-

GETS. The specifications in this section cannot be guaranteed until device characterization has taken place.]

The following specifications apply after calibration for V

= +1.9V

, OutV = 1.9V, V

FSR (a.c. coupled) = differential

860mV

P-P

= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

CLK

= 1 GHz at 0.5V

P-P

with 50% duty cycle, Non-

Extended Control Mode, R

EXT

= 3300Ω

0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for T

MIN

to T

MAX

. All other limits T

= 25˚C, unless otherwise noted. (Notes 6, 7)

Symbol Parameter Conditions

Typical

(Note 8)

Limits

(Note 8)

Units

(Limits)

DIGITAL OUTPUT CHARACTERISTICS

∆ V

Output Offset Voltage Change

Between Logic Levels

1mV

Output Short Circuit Current

Output+ & Output- connected to

0.8V

4mA

Differential Output Impedance 100 Ohms

POWER SUPPLY CHARACTERISTICS

Analog Supply Current

PD = PDQ = Low

PD = Low, PDQ = High

PD = High

627

325

4.3

690

360

mA (max)

Output Driver Supply Current

PD = PDQ = Low

PD = Low, PDQ = High

PD = PDQ = High

202

116

257

135

mA (max)

Power Consumption

PD = PDQ = Low

PD = Low, PDQ = High

PD = PDQ = High

1.6

0.84

1.8

0.94

W (max)

PSRR1 D.C. Power Supply Rejection Ratio

Change in Full Scale Error with

change in V

from 1.8V to 2.0V

73 dB

PSRR2 A.C. Power Supply Rejection Ratio 248 MHz, 50mV

P-P

riding on V

TBD dB

AC ELECTRICAL CHARACTERISTICS

CLK1

Maximum Conversion Rate

≤ 85˚C 1.1 1.0 GHz (min)

≤ 75˚C 1.3 GHz

CLK2

Minimum Conversion Rate 200 MHz

Input Clock Duty Cycle

200 MHz ≤ Input clock frequency ≤

1 GHz (Normal Mode)

% (min)

% (max)

Input Clock Duty Cycle

500MHz ≤ Input clock frequency ≤ 1

GHz (DES Mode)

% (min)

% (max)

Input Clock Low Time (Note 12) 500 200 ps (min)

Input Clock High Time (Note 12) 500 200 ps (min)

DCLK Duty Cycle (Note 12) 50

% (min)

% (max)

Reset Setup Time (Note 12) 150 TBD ps (min)

Reset Hold Time (Note 12) 250 TBD ps (min)

Syncronizing Edge to DCLK Output

Delay

CLKIN

= 1.0 GHz

CLKIN

= 200 MHz

3.53

3.85

RPW

Reset Pulse Width 4

Clock Cycles

(min)

LHT

Differential Low to High Transition

Time

10% to 90%, C

= 2.5 pF 250 ps

HLT

Differential High to Low Transition

Time

10% to 90%, C

= 2.5 pF 250 ps

OSK

DCLK to Data Output Skew

50% of DCLK transition to 50% of

Data transition, SDR Mode

and DDR Mode, 0˚ DCLK (Note 12)

200 ps (max)

Data to DCLK Set-Up Time DDR Mode, 180˚ DCLK (Note 12) 750 TBD ps (min)

ADC08D1000

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