
162
AT89C5131
4136A–USB–03/03
External Data Memory Read Cycle
Serial Port Timing - Shift
Register Mode
Table 110. Symbol Description (F = 40 MHz)
Table 111. AC Parameters for a Fix Clock (F = 40 MHz)
Table 112. AC Parameters for a Variable Clock
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
T
AVWL
T
LLWL
T
RLAZ
ADDRESS A8-A15 OR SFR P2
T
RHDZ
T
WHLH
T
RLRH
T
LLDV
T
RHDX
T
LLAX
T
AVDV
Symbol Parameter
T
XLXL
Serial port clock cycle time
T
QVHX
Output data set-up to clock rising edge
T
XHQX
Output data hold after clock rising edge
T
XHDX
Input data hold after clock rising edge
T
XHDV
Clock rising edge to input data valid
Symbol Min Max Units
T
XLXL
300 ns
T
QVHX
200 ns
T
XHQX
30 ns
T
XHDX
0ns
T
XHDV
117 ns
Symbol Type
Standard
Clock X2 Clock
X Parameter
for -M Range Units
T
XLXL
Min 12 T 6 T ns
T
QVHX
Min 10 T - x 5 T - x 50 ns
T
XHQX
Min 2 T - x T - x 20 ns
T
XHDX
Min x x 0 ns
T
XHDV
Max 10 T - x 5 T- x 133 ns
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