
ATmega163(L)
125
Figure 81. Parallel Programming
ATmega163
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0
DATA
RESET
PD7
+12 V
BS1
XA0
XA1
OE
RDY/BSY
PAGEL
PA0
WR
BS2
Table 55. Pin Name Mapping
Signal Name in Programming Mode Pin Name I/O Function
RDY/BSY
PD1 O 0: Device is busy programming, 1: Device is ready for new command
OE
PD2 I Output Enable (Active low)
WR PD3 I Write Pulse (Active low)
BS1 PD4 I Byte Select 1 (‘0’ selects low byte, ‘1’ selects high byte)
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
PAGEL PD7 I Program Memory Page Load
BS2 PA0 I Byte Select 2 (‘0’ selects low byte, ‘1’ selects 2’nd high byte)
DATA PB7-0 I/O Bidirectional Databus (Output when OE
is low)
Table 56. XA1 and XA0 Coding
XA1 XA0 Action when XTAL1 is Pulsed
0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1)
0 1 Load Data (High or Low data byte for Flash determined by BS1)
1 0 Load Command
1 1 No Action, Idle
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