109
ATmega16(L)
2466B–09/01
The input capture is updated with the counter (TCNT1) value each time an event occurs
on the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The
input capture can be used for defining the counter TOP value.
The input capture register is 16 bit in size. To ensure that both the high and low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary high byte register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 86.
Timer/Counter Interrupt Mask
Register – TIMSK
(1)
Note: 1. This register contains interrupt control bits for several timer/counters, but only timer 1
bits are described in this section. The remaining bits are described in their respective
timer sections.
• Bit 5 - TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the Timer/Counter1 input capture interrupt is enabled. The
corresponding interrupt vector (See “Interrupts” on page 42.) is executed when the ICF1
flag, located in TIFR, is set.
• Bit 4 - OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the Timer/Counter1 output compare A match interrupt is enabled. The
corresponding interrupt vector (See “Interrupts” on page 42.) is executed when the
OCF1A flag, located in TIFR, is set.
• Bit 3 - OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the Timer/Counter1 output compare B match interrupt is enabled. The
corresponding interrupt vector (See “Interrupts” on page 42.) is executed when the
OCF1B flag, located in TIFR, is set.
• Bit 2 - TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the status register is set (interrupts glo-
bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding
interrupt vector (See “Interrupts” on page 42.) is executed when the TOV1 flag, located
in TIFR, is set.
Timer/Counter Interrupt Flag
Register – TIFR
Note: This register contains flag bits for several timer/counters, but only timer 1 bits are
described in this section. The remaining bits are described in their respective timer
sections.
Bit 7654 3210
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
(27 Seiten)
(40 Seiten)
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