Rainbow-electronics ATtiny26L Bedienungsanleitung PDF herunterladen (Seite 41)

ATtiny26(L)

1477B–AVR–04/02

Power Management

and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby

saving power. The AVR provides various sleep modes allowing the user to tailor the

power consumption to the application’s requirements.

To enter any of the four sleep modes, the SE bit in MCUCR must be written to logic one

and a SLEEP instruction must be executed. The SM1, and SM0 bits in the MCUCR

by) will be activated by the SLEEP instruction. See Table 18 for a summary. If an

enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The

MCU is then halted for four cycles in addition to the start-up time, it executes the inter-

rupt routine, and resumes execution from the instruction following SLEEP. The contents

of the Register File and SRAM are unaltered when the device wakes up from sleep. If a

Reset occurs during sleep mode, the MCU wakes up and executes from the Reset

Vector.

Table 20 on page 42 presents the different clock systems in the ATtiny26, and their dis-

tribution. The figure is helpful in selecting an appropriate sleep mode.

Idle Mode When the SM1..0 bits are written to “00”, the SLEEP instruction makes the MCU enter

Idle mode, stopping the CPU but allowing Analog Comparator, ADC, USI,

Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clk

CPU

and clk

FLASH

, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and USI Start and Overflow interrupts. If wake-up

from the Analog Comparator interrupt is not required, the Analog Comparator can be

powered down by setting the ACD bit in the Analog Comparator Control and Status

enabled, a conversion starts automatically when this mode is entered.

ADC Noise Reduction Mode When the SM1..0 bits are written to “01”, the SLEEP instruction makes the MCU enter

ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Inter-

rupts, the USI start condition detection, and the Watchdog to continue operating (if

enabled). This sleep mode basically halts clk

I/O

, clk

CPU

, and clk

FLASH

, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measure-

ments. If the ADC is enabled, a conversion starts automatically when this mode is

entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a

Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an EEPROM ready

interrupt, an External Level Interrupt on INT0, or a pin change interrupt can wake up the

MCU from ADC Noise Reduction mode.

Power-down Mode When the SM1..0 bits are written to “10”, the SLEEP instruction makes the MCU enter

Power-down mode. In this mode, the External Oscillator is stopped, while the External

Interrupts, the USI start condition detection, and the Watchdog continue operating (if

enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start con-

dition interrupt, an External Level Interrupt on INT0, or a pin change interrupt can wake

up the MCU. This sleep mode basically halts all generated clocks, allowing operation of

asynchronous modules only.

When waking up from Power-down mode, there is a delay from the wake-up condition

occurs until the wake-up becomes effective. This allows the clock to restart and become

stable after having been stopped. The wake-up period is defined by the same CKSEL

Fuses that define the reset time-out period, as described in “Clock Sources” on page 27.

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