Rainbow-electronics DS1972 Bedienungsanleitung

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1 of 23 REV: 083006
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata
.
i
Button DESCRIPTION
The DS1972 is a 1024-bit, 1-Wire
®
EEPROM
organized as four memory pages of 256 bits each in
a rugged i
Button package. Data is written to an 8-
byte scratchpad, verified, and then copied to the
EEPROM memory. As a special feature, the four
memory pages can individually be write protected or
put in EPROM-emulation mode, where bits can only
be changed from a 1 to a 0 state. The DS1972
communicates over the single-conductor 1-Wire bus.
The communication follows the standard Dallas
Semiconductor 1-Wire protocol. Each device has its
own unalterable and unique 64-bit ROM registration
number that is factory lasered into the device. The
registration number is used to address the device in
a multidrop 1-Wire net environment.
APPLICATIONS
Access Control/Parking Meter
Work-In-Progress Tracking
Tool Management
Inventory Control
Maintenance/Inspection Data Storage
F5 AND F3 MicroCAN
0.51
5.89
IO
16.25
17.35
51 2D
0000006234FB
â
1-Wire
â
â
3.10
IO GND
0.51
GND
F3 size F5 size Branding
SPECIAL FEATURES
§ 1024 Bits of EEPROM Memory Partitioned into
Four Pages of 256 Bits
§ Individual Memory Pages can be Permanently
Write Protected or Put in EPROM-Emulation
Mode ("Write to 0")
§ Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
§ IEC 1000-4-2 Level 4 ESD Protection (8kV
Contact, 15kV Air, typical)
§ Reads and Writes Over a Wide Voltage Range of
2.8V to 5.25V from -40°C to +85°C
§ Communicates to Host with a Single Digital
Signal at 15.4kbps or 125kbps Using 1-Wire
Protocol
COMMON iButton FEATURES
§ Unique Factory-Lasered 64-Bit Registration
Number Assures Error-Free Device Selection
and Absolute Traceability Because No Two Parts
are Alike
§ Built-In Multidrop Controller for 1-Wire Net
§ Chip-Based Data Carrier Stores Digital Identifi-
cation and Information, Armored in a Durable
Stainless-Steel Case
§ Data can be Accessed While Affixed to Object
§ Button Shape is Self-Aligning with Cup-Shaped
Probes
§ Easily Affixed with Self-Stick Adhesive Backing,
Latched by its Flange, or Locked with a Ring
Pressed onto its Rim
§ Presence Detector Acknowledges when Reader
First Applies Voltage
§ Designed to meet UL#913 (4th Edit.); Intrinsically
Safe Apparatus: Under Entity Concept for use in
Class I, Division 1, Group A, B, C, and D
Locations, contact Dallas Semiconductor for
certification schedule
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS1972-F5# -40°C to 85°C F5 iButton
DS1972-F3# -40°C to 85°C F3 iButton
# indicates RoHS complience
Contact factory lead-free compliance
Commands, Registers, and Modes are capitalized for
clarity.
I
Button, 1-Wire, and MicroCAN are registered trademarks of Dallas
Semiconductor Corp.
DS1972
1024-Bit EEPROM i
Button
www.maxim-ic.com
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Inhaltsverzeichnis

Seite 1 - 1024-Bit EEPROM i

1 of 23 REV: 083006 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple re

Seite 2 - ELECTRICAL CHARACTERISTICS

DS1972: 1024-Bit EEPROM iButton 10 of 23 Figure 7-2. Memory Function Flow Chart (continued) AAhRead Scratch-Pad ?DS1972 sets ScratchpadByte Coun

Seite 3 - EXAMPLES OF ACCESSORIES

DS1972: 1024-Bit EEPROM iButton 11 of 23 Figure 7-3. Memory Function Flow Chart (continued) * 1-Wire idle high for powerFrom Figure 72nd PartTo

Seite 4 - OVERVIEW

DS1972: 1024-Bit EEPROM iButton 12 of 23 Figure 7-4. Memory Function Flow Chart (continued) F0hRead Memory ?Address< 90h ?YNBus Master TXTA1

Seite 5 - 64-BIT LASERED ROM

DS1972: 1024-Bit EEPROM iButton 13 of 23 READ SCRATCHPAD COMMAND [AAh] The Read Scratchpad command allows verifying the target address and the i

Seite 6 - Figure 5. Memory Map

DS1972: 1024-Bit EEPROM iButton 14 of 23 The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the

Seite 7 - Figure 6. Address Registers

DS1972: 1024-Bit EEPROM iButton 15 of 23 SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of dev

Seite 8 - T2:T0

DS1972: 1024-Bit EEPROM iButton 16 of 23 Figure 9-1. ROM Functions Flow Chart From Figure 92nd PartTo Memory FunctionsFlow Chart (Figure 7)Mast

Seite 9 - 9 of 23

DS1972: 1024-Bit EEPROM iButton 17 of 23 Figure 9-2. ROM Functions Flow Chart (continued) To Figure 9 1st Part From Figure 9 1st Part From Fig

Seite 10 - 10 of 23

DS1972: 1024-Bit EEPROM iButton 18 of 23 1-Wire SIGNALING The DS1972 requires strict protocols to ensure data integrity. The protocol consists o

Seite 11 - 11 of 23

DS1972: 1024-Bit EEPROM iButton 19 of 23 Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the VTH thre

Seite 12 - 12 of 23

DS1972: 1024-Bit EEPROM iButton 2 of 23 ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.5V, +6V I/O Sink Current 20mA Operating Temperature Range

Seite 13 - HARDWARE CONFIGURATION

DS1972: 1024-Bit EEPROM iButton 20 of 23 Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line

Seite 14 - TRANSACTION SEQUENCE

DS1972: 1024-Bit EEPROM iButton 21 of 23 CRC GENERATION With the DS1972 there are two different types of CRCs. One CRC is an 8-bit type and is

Seite 15 - OVERDRIVE-MATCH ROM [69h]

DS1972: 1024-Bit EEPROM iButton 22 of 23 COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—LEGEND SYMBOL DESCRIPTION RST 1-Wire Reset Pulse genera

Seite 16 - 16 of 23

DS1972: 1024-Bit EEPROM iButton 23 of 23 MEMORY FUNCTION EXAMPLE Write to the first 8 bytes of memory page 1. Read the entire memory. With only

Seite 17 - 17 of 23

DS1972: 1024-Bit EEPROM iButton 3 of 23 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG (Note 5, 19)

Seite 18 - Read-/Write-Time Slots

DS1972: 1024-Bit EEPROM iButton 4 of 23 DESCRIPTION The DS1972 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user

Seite 19 - Master-to-Slave

DS1972: 1024-Bit EEPROM iButton 5 of 23 Figure 2. Hierarchical Structure for 1-Wire Protocol Available Commands: DS1972 Command Level: Data

Seite 20 - Slave-to-Master

DS1972: 1024-Bit EEPROM iButton 6 of 23 Figure 5. Memory Map ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES 0000h to 001Fh R/(W) Data Mem

Seite 21 - CRC GENERATION

DS1972: 1024-Bit EEPROM iButton 7 of 23 The protection control registers determine how incoming data on a Write Scratchpad command is loaded in

Seite 22

DS1972: 1024-Bit EEPROM iButton 8 of 23 WRITING WITH VERIFICATION To write data to the DS1972, the scratchpad has to be used as intermediate sto

Seite 23 - MEMORY FUNCTION EXAMPLE

DS1972: 1024-Bit EEPROM iButton 9 of 23 Figure 7-1. Memory Function Flow Chart 0Fh Write Scratch- pad ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8

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