Rainbow-electronics MAX109 Bedienungsanleitung PDF herunterladen (Seite 6)

MAX109

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

6 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

A = V

I = V

D = 5V, V

O = 3.3V, V

= -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f

CLK

= 2.2Gsps, analog input

amplitude at -1dBFS differential, clock input amplitude 400mV

P-P

differential, digital output pins differential R

= 100Ω. Typical values

are at T

= +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SFDR

300

= 300MHz, f

CLK

= 2.2Gsps 61.7

SFDR

1000

= 1000MHz, f

CLK

= 2.2Gsps (Note 8) 44.4 51.1

SFDR

1600

= 1600MHz, f

CLK

= 2.2Gsps (Note 8) 43.7 50.3

SFDR

2500

= 2500MHz, f

CLK

= 2.2Gsps 45.0

SFDR

500

= 500MHz, f

CLK

= 2.5Gsps 53.7

Spurious Free Dynamic Range

SFDR

1600

= 1600MHz, f

CLK

= 2.5Gsps 44.6

dBc

SINAD

300

= 300MHz, f

CLK

= 2.2Gsps 44.1

SINAD

1000

= 1000MHz, f

CLK

= 2.2Gsps (Note 8) 40.4 43.1

SINAD

1600

= 1600MHz, f

CLK

= 2.2Gsps (Note 8) 37.9 42.1

SINAD

2500

= 2500MHz, f

CLK

= 2.2Gsps 40.1

SINAD

500

= 500MHz, f

CLK

= 2.5Gsps 43.1

Signal-to-Noise-Plus-Distortion

Ratio

SINAD

1600

= 1600MHz, f

CLK

= 2.5Gsps 40.5

Third-Order Intermodulation IM3 f

IN1

= 1590MHz, f

IN2

= 1610MHz at -7dBFS -60 dBc

Metastability Probability 10

-14

TIMING CHARACTERISTICS

Maximum Sample Rate f

CLK

(

MAX

)

2.2 Gsps

Clock Pulse-Width Low t

PWL

CLK

= t

PWL

+ t

PWH

(Note 8) 180 ps

Clock Pulse-Width High t

PWH

CLK

= t

PWL

+ t

PWH

(Note 8) 180 ps

Aperture Delay t

200 ps

Aperture Jitter t

0.2 ps

Reset Input Data Setup Time t

(Note 8) 300 ps

Reset Input Data Hold Time t

(Note 8) 250 ps

PD1

DCO = f

CLK

/ 4, CLK fall to DCO rise time 1.6

PD1DDR

DCO = f

CLK

/ 8, DDR mode, CLK fall to

DCO rise time

1.6

CLK-to-DCO Propagation Delay

PD1QDR

DCO = f

CLK

/ 16, QDR mode, CLK fall to

DCO rise time

1.6

PD2

DCO = f

CLK

/ 4, DCO rise to data transition

(Note 8)

-520 +520

PD2DDR

DCO = f

CLK

/ 8, DDR mode, DCO rise to

data transition (Note 8)

-520 +

CLK

520 +

CLK

DCO-to-Data Propagation Delay

PD2QDR

DCO = f

CLK

/ 16, QDR mode, DCO rise to

data transition (Note 8)

-520 +

CLK

520 +

CLK

DCO Duty Cycle Clock mode independent

45 to

1 2 3 4 5 6 7 8 9 10 11 ... 28 29

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